专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08848472B2 Fabrication and testing method for nonvolatile memory devices 有权
标题翻译：非易失性存储器件的制造和测试方法
公开(公告)号：US08848472B2
公开(公告)日：2014-09-30
申请号：US13711850
申请日：2012-12-12
申请人： Samsung Electronics Co., Ltd.
发明人： Hiroshi Sugawara
IPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , H01L21/66 , G11C29/00 , G01R31/27 , G11C29/08 , G11C29/12 , G11C29/26 , G11C5/04 , G11C16/00 , G11C16/04
CPC分类号： H01L22/00 , G01R31/275 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C16/00 , G11C16/0483 , G11C29/006 , G11C29/08 , G11C29/12005 , G11C29/26 , G11C2029/1206 , H01L22/32 , H01L2224/48091 , H01L2224/49113 , H01L2924/00014
摘要： A plurality of master chips are arranged in a row on the wafer, each master chip including a power supply circuit providing a power supply voltage, and a plurality of slave chips are arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing.
摘要翻译：多个主芯片在晶片上排成一行，每个主芯片包括提供电源电压的电源电路，并且多个从芯片被布置在列中至少在相应的主芯片的至少一侧多个主芯片，每个从芯片包括在晶片级测试期间响应于相应主芯片提供的电源电压而功能地工作的存储单元阵列。

72. 发明授权

US08674501B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US08674501B2
公开(公告)日：2014-03-18
申请号：US12659462
申请日：2010-03-09
申请人： Yasuhide Sosogi
发明人： Yasuhide Sosogi
IPC分类号： H01L23/498
CPC分类号： G11C5/063 , G11C5/025 , G11C2029/1206 , H01L23/5286 , H01L27/0203 , H01L27/105 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.
摘要翻译：半导体集成电路器件包括多个电路单元，每个电路单元具有多个逻辑电路; 以及从外部向半导体集成电路装置供电的多个电源端子，其中，具有多个逻辑电路的多个电路单元具有相互具有共同的封装设计，以及各电路单元的垂直方向和横向的长度具有多个逻辑电路等于彼此相邻的电源端子之间的距离的偶数倍。

73. 发明申请

US20130148402A1 CONTROL SCHEME FOR 3D MEMORY IC 有权
标题翻译： 3D存储IC控制方案
公开(公告)号：US20130148402A1
公开(公告)日：2013-06-13
申请号：US13524980
申请日：2012-06-15
申请人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
发明人： Meng-Fan CHANG , Wei-Cheng Wu , Tsung-Hsien Huang , Chien-Yuan Chen
IPC分类号： G11C5/06
CPC分类号： G11C29/023 , G11C8/08 , G11C11/417 , G11C29/028 , G11C29/04 , G11C29/26 , G11C2029/1202 , G11C2029/1206 , G11C2029/2602
摘要： The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
摘要翻译：本发明公开了一种包括主芯片和至少一个从芯片的3D存储器IC的控制方案。主芯片包括主存储器核心，第一本地定时器，I / O缓冲器，第一焊盘和第二焊盘。至少一个从芯片与主芯片堆叠。每个从芯片包括从存储器核心，第二本地定时器和第三焊盘。第一TSV耦合到第一焊盘和第三焊盘。逻辑控制电路层包括逻辑控制电路和第四焊盘，逻辑控制电路耦合到第四焊盘。第二TSV耦合到第二焊盘和第四焊盘。

74. 发明申请

US20130070547A1 MEMORY SYSTEM WITH A LAYER COMPRISING A DEDICATED REDUNDANCY AREA 有权
标题翻译：具有包含专用冗余区域的层的记忆系统
公开(公告)号：US20130070547A1
公开(公告)日：2013-03-21
申请号：US13621486
申请日：2012-09-17
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G11C29/24
CPC分类号： G11C29/785 , G11C29/44 , G11C2029/1206 , G11C2029/4402
摘要： Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.
摘要翻译：公开了可以包括包括第一冗余存储器元件，输入/输出接口，第一层保险丝盒和保险丝熔断控制的第一层的系统和方法。这些系统和方法还可以包括通过包括耦合到第一冗余存储器元件的第二层存储器元件和第二层熔丝盒的第一连接耦合到第一层的第二层。此外，这些系统和方法还可以包括耦合到第一层的冗余寄存器，其中当第二层存储器元件的一部分出现故障时，冗余寄存器向熔丝熔断控制提供信息，其分配第一冗余存储器的一部分元件，以通过在第一层熔丝盒和第二层熔丝盒中吹入元件来为第二层存储元件的故障部分提供冗余。

75. 发明申请

US20120294080A1 MEMORY DEVICE AND METHOD FOR DRIVING MEMORY DEVICE 有权
标题翻译：用于驱动存储器件的存储器件和方法
公开(公告)号：US20120294080A1
公开(公告)日：2012-11-22
申请号：US13472549
申请日：2012-05-16
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： G11C11/40
CPC分类号： G11C11/4085 , G11C8/12 , G11C29/12005 , G11C29/26 , G11C2029/1206
摘要： A memory device according to the invention can be operated with a single potential, by which the use of a voltage converter can be excluded, leading to the reduction of power consumption. Such an operation can be achieved by utilizing capacitive coupling of a capacitor connected to a gate of a transistor for data writing. That is, the capacitive coupling is induced by inputting a signal, which is supplied by a delay circuit configured to delay a write signal having a potential equal to the power supply potential, to the capacitor. Increase in the potential of the gate by the capacitive coupling allows the transistor to be turned on in association with the power supply potential applied to the gate from a power supply. Data is written by inputting a signal having a potential equal to the power supply potential or a grounded potential to a node through the transistor.
摘要翻译：根据本发明的存储器件可以以单个电位工作，通过该电位可以排除使用电压转换器，导致功耗的降低。这种操作可以通过利用连接到晶体管的栅极的电容器进行数据写入的电容耦合来实现。也就是说，通过输入由延迟电路提供的信号来感应电容耦合，该延迟电路被配置为将具有等于电源电位的电位的写入信号延迟到电容器。通过电容耦合增加栅极的电位使晶体管与从电源施加到栅极的电源电位相关联地导通。通过晶体管将具有等于电源电位的电位或接地电位的信号输入到节点来写入数据。

76. 发明授权

US07806324B1 Methods of making and using memory card with enhanced testability 有权
标题翻译：制作和使用存储卡的方法具有增强的可测试性
公开(公告)号：US07806324B1
公开(公告)日：2010-10-05
申请号：US12019161
申请日：2008-01-24
申请人： Khushrav S. Chhor , Tae-Hee Lee
发明人： Khushrav S. Chhor , Tae-Hee Lee
IPC分类号： G06K5/00
CPC分类号： G11C29/48 , G11C5/04 , G11C29/1201 , G11C2029/1206 , H01L2224/48227
摘要： By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.
摘要翻译：通过减少存储卡中支持实际存储单元所需的卡片基板的数量，通常在卡的最终组装之前通常被去除的卡的测试接口可以被带到成品卡的允许长度内，并且可以因此，永久保留在卡上。因此，在现场故障的情况下，测试接口仍然可用于测试卡并诊断故障的位置和原因。

77. 发明授权

US07449909B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07449909B2
公开(公告)日：2008-11-11
申请号：US11707408
申请日：2007-02-16
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

78. 发明授权

US07242208B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07242208B2
公开(公告)日：2007-07-10
申请号：US11386512
申请日：2006-03-22
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/02 , G01R31/28
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

79. 发明授权

US07119567B2 System and method for testing one or more dies on a semiconductor wafer 有权
标题翻译：用于测试半导体晶片上的一个或多个管芯的系统和方法
公开(公告)号：US07119567B2
公开(公告)日：2006-10-10
申请号：US10243544
申请日：2002-09-12
申请人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
发明人： David SuitWai Ma , Tao Wang , James J. Dietz , Bing Ren
IPC分类号： G01R31/26 , G01R31/28 , G01R31/02
CPC分类号： G01R31/3193 , G01R31/31707 , G01R31/31718 , G01R31/318511 , G11C29/006 , G11C29/40 , G11C2029/1206 , G11C2029/2602
摘要： A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.
摘要翻译：测试系统或方法将半导体晶片中的一个或多个管芯的读取数据与写入一个或多个管芯的原始数据进行比较。测试系统包括连接到半导体晶片上的一个或多个管芯的一个或多个写入寄存器。一个或多个比较器连接到管芯和写入寄存器。比较器响应原始数据和读取数据产生结果。

80. 发明授权

US06925589B1 Method for translating physical cell-coordinates of a memory product to n-dimensional addresses 失效
标题翻译：将存储产品的物理单元坐标转换为n维地址的方法
公开(公告)号：US06925589B1
公开(公告)日：2005-08-02
申请号：US09488865
申请日：2000-01-21
申请人： Daniel Ben-Ezri
发明人： Daniel Ben-Ezri
IPC分类号： G11R31/28
CPC分类号： G11C29/54 , G11C29/44 , G11C29/56008 , G11C2029/0403 , G11C2029/1206 , G11C2029/1806
摘要： A structure and method for translating address buffer coordinates for a device under test having two or more similar repeatable units. The method comprises identifying a repeatable unit of the repeatable units, preparing a look up table for translating buffer coordinates of a reference unit of the repeatable units and displacing information from the look up table to correspond to the repeatable units.
摘要翻译：用于翻译被测设备的地址缓冲器坐标的结构和方法具有两个或更多个类似的可重复单元。该方法包括识别可重复单元的可重复单元，准备用于翻译可重复单元的参考单元的缓冲器坐标的查找表和从查找表移位信息以对应于可重复单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式