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71. 发明授权

US07385855B2 Nonvolatile memory device having self reprogramming function 有权
标题翻译：具有自重新编程功能的非易失性存储器件
公开(公告)号：US07385855B2
公开(公告)日：2008-06-10
申请号：US11306370
申请日：2005-12-26
申请人： Ching-Yuan Lin , Chien-Liang Kuo
发明人： Ching-Yuan Lin , Chien-Liang Kuo
IPC分类号： G11C16/06
CPC分类号： G11C29/52 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/12 , G11C29/1201 , G11C2029/1204
摘要： A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The memory cell is for data storage. The first transistor receives a reading control signal at a gate. And a first source/drain is electrically coupled to the memory cell. The second transistor receives a reset control signal at a gate. A source/drain is electrically coupled to a second source/drain of the first transistor, and a second source/drain of the second transistor is grounded. In addition, the electrical characteristics of the second transistor are opposite to that of the first transistor. The latch circuit includes a latch input terminal and a latch output terminal. In which, the latch input terminal is electrically coupled to the second source/drain of the first transistor and the first source/drain of the second transistor.
摘要翻译：提供了具有自重新编程功能的非易失性存储装置。非易失性存储器件包括存储单元，第一晶体管，第二晶体管和锁存电路。存储单元用于数据存储。第一晶体管在门处接收读取控制信号。并且第一源极/漏极电耦合到存储器单元。第二晶体管在门处接收复位控制信号。源极/漏极电耦合到第一晶体管的第二源极/漏极，并且第二晶体管的第二源极/漏极接地。此外，第二晶体管的电特性与第一晶体管的电特性相反。锁存电路包括锁存输入端和锁存输出端。其中，锁存器输入端子电耦合到第一晶体管的第二源极/漏极和第二晶体管的第一源极/漏极。

72. 发明申请

US20080130387A1 METHOD FOR EVALUATING MEMORY CELL PERFORMANCE 失效
标题翻译：评估记忆体性能的方法
公开(公告)号：US20080130387A1
公开(公告)日：2008-06-05
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译：用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作。该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。弱写入条件和/或弱写入条件可以通过选择性加载来测量。

73. 发明授权

US07382670B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07382670B2
公开(公告)日：2008-06-03
申请号：US11669420
申请日：2007-01-31
申请人： Tomohito Kawano , Hidetoshi Saito
发明人： Tomohito Kawano , Hidetoshi Saito
IPC分类号： G11C7/00
CPC分类号： G11C29/34 , G11C16/04 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.
摘要翻译：公开了一种具有用于写入的第一和第二负载电路的半导体集成电路器件。在所有位应力测试时，从第一和第二负载电路提供用于写入的高电压用于写入所有位线。在进行偶数位应力测试时，写入的高电压从第一负载电路提供给偶数位线，并且比写入的高电压低的电位从第二负载电路提供给写入奇数位线。在奇数位应力测试时，较低的电位从第一负载电路提供给偶数位线，并且用于写入的高电压从第二负载电路提供给奇数位线。

74. 发明申请

US20080062767A1 METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A READ CHARGE VOLTAGE AND A READ DISCRIMINATING VOLTAGE IN A NON-VOLATILE NAND TYPE MEMORY DEVICE 审中-公开
标题翻译：固定读取评估时间的方法或读取电荷电压与非易失性NAND型存储器件中的读取分辨电压之间的差异
公开(公告)号：US20080062767A1
公开(公告)日：2008-03-13
申请号：US11854713
申请日：2007-09-13
申请人： Luca CRIPPA , Roberto RAVASIO , Rino MICHELONI
发明人： Luca CRIPPA , Roberto RAVASIO , Rino MICHELONI
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C16/04 , G11C29/023 , G11C29/025 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： The evaluation time or the difference between the read charge voltage and the read discrimination voltage of the programmed or erased state of a cell of a NAND memory array is set for the individual memory device. This is done in such a way that at least partially compensates the generally large spread of parasitic capacitance values of the array bitlines in the mass production fabrication process of the NAND memory array.
摘要翻译：针对各个存储器件设置评估时间或NAND存储器阵列的单元的编程或擦除状态的读取充电电压和读取判别电压之间的差。这样做的方式是至少部分地补偿NAND存储器阵列的批量生产制造过程中阵列位线的寄生电容值的普遍大的扩展。

75. 发明申请

US20070159900A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20070159900A1
公开(公告)日：2007-07-12
申请号：US11616452
申请日：2006-12-27
申请人： Mamoru AOKI
发明人： Mamoru AOKI
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C29/02 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C2029/1204
摘要： Disclosed is a semiconductor memory device includes two equalizing elements, each connected between a pair of bit lines and being separately subjected to on/off control by respective control signals. When performing a test, one of the control signals is kept HIGH and the other of the control signal is kept LOW during a precharge period, and activation/deactivation of the two equalizing elements is separately controlled. A failure such as a defect in one of the two equalizing elements subjected to the on/off control by the control signal can be thereby detected.
摘要翻译：公开了一种半导体存储器件，其包括两个均衡元件，每个均衡元件连接在一对位线之间，并通过相应的控制信号分别进行开/关控制。当进行测试时，控制信号之一保持为高，并且在预充电期间控制信号中的另一个保持为低电平，并且分别控制两个均衡元件的激活/去激活。因此，能够检测出受到控制信号的接通/断开控制的两个均衡元件之一的缺陷的故障。

76. 发明申请

US20070145981A1 SEMICONDUCTOR LEAKAGE CURRENT DETECTOR AND LEAKAGE CURRENT MEASUREMENT METHOD, SEMICONDUCTOR LEAKAGE CURRENT DETECTOR WITH VOLTAGE TRIMMING FUNCTION AND REFERENCE VOLTAGE TRIMMING METHOD, AND SEMICONDUCTOR INTERGRATED CIRCUIT THEREOF 有权
标题翻译：半导体漏电流检测器和泄漏电流测量方法，具有电压调制功能的半导体漏电流检测器和参考电压调制方法及其半导体集成电路
公开(公告)号：US20070145981A1
公开(公告)日：2007-06-28
申请号：US11614127
申请日：2006-12-21
申请人： Yasuhiro TOMITA , Manabu KOMIYA , Hitoshi SUWA , Toshiki MORI
发明人： Yasuhiro TOMITA , Manabu KOMIYA , Hitoshi SUWA , Toshiki MORI
IPC分类号： G01R31/14
CPC分类号： G01R31/3008 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor
摘要翻译：本发明的半导体泄漏电流检测器包括使得测量电流流动或切断的第一模拟开关，引起参考电流流动或被切断的第二模拟开关，积分电容元件其通过第一模拟开关和第二模拟开关连接，并对被测量电流或参考电流进行充电;放电单元，其对积分电容器进行放电;以及比较单元，其将参考电压与积分电压积分电容器中产生的电压通过积分电容器放电后的基准电流产生，积分电容元件中产生的积分电压由积分电容器放电后的被测电流

77. 发明申请

US20070109834A1 Ferroelectric memory to be tested by applying disturbance voltage to a plurality of ferroelectric capacitors at once in direction to weaken polarization, and method of testing the same 失效
标题翻译：通过在多个强电介质电容器上施加干扰电压以便弱化极化的方向进行测试的铁电存储器及其测试方法
公开(公告)号：US20070109834A1
公开(公告)日：2007-05-17
申请号：US11417154
申请日：2006-05-04
申请人： Ryu Ogiwara , Daisaburo Takashima
发明人： Ryu Ogiwara , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/223 , G11C29/06 , G11C29/08 , G11C29/12005 , G11C2029/1204
摘要： A unit cell is formed by a ferroelectric capacitor and first MOS transistor, and a block is formed by connecting a plurality of unit cells in series. The gates of the first MOS transistors in the individual unit cells are connected to word lines, which are selectively driven by a word line driver on the basis of a row address signal. A plate line is connected to one terminal of the block, and driven by a plate line driver. A bit line is connected to the other terminal of the block via a second MOS transistor for block selection, and selected by a column decoder on the basis of a column address. A driver/controller controls the plate line driver and column decoder to apply a potential difference between the plate line and bit line, while a plurality of word lines are kept off.
摘要翻译：单元由铁电电容器和第一MOS晶体管形成，并且通过串联连接多个单元电池而形成块。单个单元电池中的第一MOS晶体管的栅极连接到字线，该字线由字线驱动器基于行地址信号选择性地驱动。板线连接到块的一个端子，并由板线驱动器驱动。位线通过用于块选择的第二MOS晶体管连接到块的另一端，并且由列解码器基于列地址选择。驱动器/控制器控制板线驱动器和列解码器以在板线和位线之间施加电位差，同时多个字线被保持关闭。

78. 发明申请

US20070047355A1 METHOD FOR DETECTING A LEAKAGE CURRENT OF A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于检测半导体存储器的泄漏电流的方法
公开(公告)号：US20070047355A1
公开(公告)日：2007-03-01
申请号：US11467740
申请日：2006-08-28
申请人： Herbert Benzinger , Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
发明人： Herbert Benzinger , Tobias Graf , Joerg Kliewer , Manfred Proell , Stephan Schroeder
IPC分类号： G11C7/02
CPC分类号： G11C11/4078 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/02 , G11C2029/1204 , G11C2029/5006 , G11C2207/005
摘要： A method for detecting a leakage current in a bit line of a semiconductor memory is disclosed. In one embodiment, the method includes isolating the connection of a sense amplifier from a bit line via an isolation transistor, reading out a memory cell to the bit line, waiting until a predetermined delay time has elapsed, so that a leakage current measurably changes the voltage on the bit line within the delay time. The sense amplifier is short circuited with the bit line via the isolation transistor. The voltage on the bit line is collected by the sense amplifier, and compared with a reference voltage so as to detect the leakage current.
摘要翻译：公开了一种用于检测半导体存储器的位线中的漏电流的方法。在一个实施例中，该方法包括经由隔离晶体管将读出放大器与位线的连接隔离，将存储器单元读出到位线，等待直到经过预定的延迟时间，使得漏电流可测量地改变延迟时间内位线上的电压。读出放大器通过隔离晶体管与位线短路。位线上的电压由读出放大器收集，并与参考电压进行比较，以便检测漏电流。

79. 发明授权

US07158426B2 Method for testing an integrated semiconductor memory 有权
标题翻译：用于测试集成半导体存储器的方法
公开(公告)号：US07158426B2
公开(公告)日：2007-01-02
申请号：US11121175
申请日：2005-05-04
申请人： Koen van der Zanden , Manfred Pröll , Jörg Kliewer , Björn Wirker
发明人： Koen van der Zanden , Manfred Pröll , Jörg Kliewer , Björn Wirker
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50 , G11C11/401 , G11C29/12015 , G11C29/50012 , G11C2029/1204 , G11C2029/2602
摘要： An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control signal and starts a test run independent of the control clock. Driving with the first control signal, selection transistors in a memory bank that can be selected by a memory bank address are turned off. Afterward, bit lines in the selected memory bank are interconnected and driven with a predetermined precharge potential. After a precharge time has elapsed, one of the word lines is selected by an applied word line address and the selection transistors in the selected memory bank connected to the selected word line are turned on. Precharge times are set and tested independently of the clock period of the control clock.
摘要翻译：集成半导体存储器可以在与控制时钟同步的正常操作状态下操作。在测试操作状态下，集成半导体存储器与第一控制信号的控制时钟的时钟边沿同步地驱动，并独立于控制时钟启动测试运行。利用第一控制信号驱动，可以由存储体地址选择的存储体中的选择晶体管截止。之后，所选择的存储体中的位线被互连并以预定的预充电势驱动。在预充电时间过去之后，通过应用的字线地址选择一个字线，并且连接到所选字线的所选存储体中的选择晶体管导通。独立于控制时钟的时钟周期设置和测试预充电时间。

80. 发明授权

US07142442B1 Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权
标题翻译：具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案
公开(公告)号：US07142442B1
公开(公告)日：2006-11-28
申请号：US10796750
申请日：2004-03-08
申请人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
发明人： Vasisht Mantra Vadi , David P. Schultz , Steven P. Young , Jennifer Wong
IPC分类号： G11C5/06 , G11C8/00 , G11C7/00
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译：存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。

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