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71. 发明授权

US08527438B2 Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array 有权
标题翻译：在超密集突触交叉阵列中产生尖峰时序依赖性可塑性
公开(公告)号：US08527438B2
公开(公告)日：2013-09-03
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

72. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

73. 发明申请

US20120120701A1 TERNARY CONTENT ADDRESSABLE MEMORY USING PHASE CHANGE DEVICES 审中-公开
标题翻译：使用相位变更设备的内容可寻址存储器
公开(公告)号：US20120120701A1
公开(公告)日：2012-05-17
申请号：US13350823
申请日：2012-01-16
申请人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
发明人： Brian L. Ji , Chung H. Lam , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing ternary data values of high, low, and don't care. An aspect of the content addressable memory device is the use of first memory elements and second memory elements in the memory cells. The first and second memory elements are electrically coupled in parallel circuit to a match-line. The first memory elements are coupled to first word-lines and the second memory elements are coupled to second word-lines. The first memory elements are configured to store low resistance states if the ternary data value is low and high resistance states if the ternary data value is either high or don't care. The second memory elements are configured to store the low resistance states if the ternary data value is high and the high resistance states if the ternary data value is either low or don't care.
摘要翻译：一种具有多个存储单元的内容可寻址存储器件，其存储高，低和不关心的三进制数据值。内容可寻址存储器件的一个方面是在存储器单元中使用第一存储器元件和第二存储器元件。第一和第二存储器元件以并联电路电耦合到匹配线。第一存储器元件耦合到第一字线，并且第二存储器元件耦合到第二字线。如果三进制数据值低，则第一存储器元件被配置为存储低电阻状态，并且如果三进制数据值高或不在乎，则高电阻状态。如果三进制数据值高，则第二存储器元件被配置为存储低电阻状态，并且如果三进制数据值为低或不关心，则存在高电阻状态。

74. 发明申请

US20110119215A1 HARDWARE ANALOG-DIGITAL NEURAL NETWORKS 有权
标题翻译：硬件模拟数字神经网络
公开(公告)号：US20110119215A1
公开(公告)日：2011-05-19
申请号：US12618101
申请日：2009-11-13
申请人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
发明人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
IPC分类号： G06N3/06
CPC分类号： G06N3/0635 , G06N3/063
摘要： An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
摘要翻译：模拟数字交叉点网络包括多个行和列，多个突触节点，多个突触节点中的每个突触节点设置在多个行和列的行和列的交点处，其中每个突触所述多个突触节点的节点包括与其相关联的权重，与所述多个列中的每列相关联的列控制器，其中每个列控制器被设置为使能与所述列控制器通信的突触节点处的权重变化，以及与多个行的每一行相关联的行控制器，其中每个行控制器被设置为控制与所述行控制器通信的突触节点处的权重变化。

75. 发明授权

US07872889B2 High density ternary content addressable memory 有权
标题翻译：高密度三元内容可寻址内存
公开(公告)号：US07872889B2
公开(公告)日：2011-01-18
申请号：US12427484
申请日：2009-04-21
申请人： Chung H. Lam , Bipin Rajendran
发明人： Chung H. Lam , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C11/5678 , G11C13/0004
摘要： A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value.
摘要翻译：一种具有存储数据字的多个存储器单元的内容可寻址存储器件。数据字中的每个数据位被设置为第一二进制值，第二二进制值和不关心值的三个值之一。内容可寻址存储器件的一个方面是在存储器单元中使用单个存储器元件和存取器件。存储器单元被布置成使得每个存储器单元电耦合到单个位线，单个匹配线和单个字线。如果数据位值是第一个二进制值，则存储器单元中的存储元件存储低电阻状态，如果数据位值是第二个二进制值则为高电阻状态，如果数据位值为“ 关心价值。

76. 发明授权

US07751217B2 Content addressable memory using phase change devices 有权
标题翻译：内容可寻址内存使用相变设备
公开(公告)号：US07751217B2
公开(公告)日：2010-07-06
申请号：US12166311
申请日：2008-07-01
申请人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
发明人： Chung H. Lam , Brian L. Ji , Robert K. Montoye , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C13/0004 , G11C15/046
摘要： Content addressable memory device utilizing phase change devices. An aspect of the content addressable memory device is the use of a comparatively lower power search-line access element and a comparatively higher power word-line access element. The word-line access element is only utilized during write operations and the search-line access element is only utilized during search operations. The word-line access element being electrically coupled to a second end of a phase change memory element and a word-line. The search-line access element also being electrically coupled to the second end of the phase change memory element and a search-line. The search-line being electrically coupled to a match-line. A bit-line is electrically coupled to a first end of the phase change memory element. Additionally, a complementary set of access elements, a complementary phase change memory element, a complementary search-line, and a complementary bit-line are also included in the content addressable memory device.
摘要翻译：使用相变装置的内容寻址存储装置。内容可寻址存储器件的一个方面是使用相对较低功率的搜索线访问元件和相对较高功率的字线访问元件。字线访问元件仅在写入操作期间使用，并且搜索线访问元件仅在搜索操作期间被使用。字线访问元件电耦合到相变存储器元件的第二端和字线。搜索线访问元件还电耦合到相变存储元件的第二端和搜索线。搜索线电耦合到匹配线。位线电耦合到相变存储元件的第一端。此外，内容可寻址存储器件中还包括互补的一组存取元件，互补相变存储器元件，互补搜索线和互补位线。

77. 发明申请

US20090052230A1 INTEGRATED CIRCUIT INCLUDING SILICIDE REGION TO INHIBIT PARASITIC CURRENTS 有权
标题翻译：集成电路，其中包括硅化物区域禁止残留电流
公开(公告)号：US20090052230A1
公开(公告)日：2009-02-26
申请号：US11843044
申请日：2007-08-22
申请人： Bipin Rajendran , Shoaib Hasan Zaidi
发明人： Bipin Rajendran , Shoaib Hasan Zaidi
IPC分类号： G11C11/00 , H01L21/00 , H01L29/02
CPC分类号： H01L27/1021 , G11C13/0004 , G11C2213/72 , H01L27/24
摘要： An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode.
摘要翻译：公开了一种集成电路。一个实施例包括耦合到第一二极管和第二二极管的第一二极管，第二二极管和半导体线。该线包括在第一二极管和第二二极管之间的第一硅化物区域。

78. 发明授权

US08331164B2 Compact low-power asynchronous resistor-based memory read operation and circuit 有权
标题翻译：紧凑型低功耗基于异步电阻的存储器读操作和电路
公开(公告)号：US08331164B2
公开(公告)日：2012-12-11
申请号：US12960651
申请日：2010-12-06
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

79. 发明申请

US20120140554A1 COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
标题翻译：紧凑型低功耗异步电动势记忆读取操作和电路
公开(公告)号：US20120140554A1
公开(公告)日：2012-06-07
申请号：US12960651
申请日：2010-12-06
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

80. 发明授权

US07881089B2 Coding techniques for improving the sense margin in content addressable memories 有权
标题翻译：用于改善内容可寻址存储器中的检测边缘的编码技术
公开(公告)号：US07881089B2
公开(公告)日：2011-02-01
申请号：US12392049
申请日：2009-02-24
申请人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
发明人： Michele M. Franceschini , Chung H. Lam , Luis A. Lastras , Bipin Rajendran
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/1006 , G11C13/0004 , G11C15/02 , G11C15/046
摘要： A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.
摘要翻译：使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值。

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