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71. 发明授权

US06265780B1 Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit 有权
标题翻译：用于集成电路中多级互连的布线结构的双镶嵌结构
公开(公告)号：US06265780B1
公开(公告)日：2001-07-24
申请号：US09203035
申请日：1998-12-01
申请人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Yimin Huang , Water Lur , Shih-Wei Sun
IPC分类号： H01L2348
CPC分类号： H01L21/76832 , H01L21/7681 , H01L21/76813 , H01L21/76835
摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.
摘要翻译：提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的介电层和蚀刻停止层。利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

72. 发明授权

US06254676B1 Method for manufacturing metal oxide semiconductor transistor having raised source/drain 有权
标题翻译：制造具有升高的源极/漏极的金属氧化物半导体晶体管的方法
公开(公告)号：US06254676B1
公开(公告)日：2001-07-03
申请号：US09340969
申请日：1999-06-28
申请人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
发明人： Gwo-Shii Yang , Michael W C Huang , Chien Chao Huang , Hsien-Ta Chung , Tri-Rung Yew
IPC分类号： C30B2514
CPC分类号： H01L29/6659 , H01L21/02532 , H01L21/02639 , H01L21/28035 , H01L29/41775 , H01L29/41783 , H01L29/6656 , H01L29/66628 , Y10S438/981
摘要： A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
摘要翻译：描述了具有升高的源极/漏极的金属氧化物半导体晶体管的制造方法。在栅电极的侧壁上形成第一间隔物。然后在衬底的暴露表面和栅电极的顶表面上形成外延层。然后在使用栅电极和第一间隔件作为第一掩模的同时在衬底上执行光注入步骤。此后，在栅电极的侧壁上形成第二间隔物。然后在使用栅电极，第一间隔物和第二间隔物作为第二掩模的同时在衬底上执行沉重的注入步骤。然后在形成源极/漏极的延伸结构之前形成外延层。因此，源/漏扩展结构中的掺杂剂避免了形成外延层所需的高温，从而防止掺杂剂的再分布。

73. 发明授权

US06221746B1 Method for forming a poly gate structure 有权
标题翻译：多栅结构的形成方法
公开(公告)号：US06221746B1
公开(公告)日：2001-04-24
申请号：US09223010
申请日：1998-12-30
申请人： Michael WC Huang , Tri-Rung Yew
发明人： Michael WC Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28176 , H01L21/32105 , H01L21/32136
摘要： A method for forming a poly gate structure is disclosed. The method comprises forming a dielectric layer on a substrate and then forming a polysilicon layer on the dielectric layer. A metal silicide layer is then formed on the polysilicon layer and, just after formation of metal silicide is accomplished completely, an annealing process is practiced to induce phase transformation of metal silicide layer. Afterwards, a passivation layer is formed over the metal silicide layer, and then a standard photolithography method is applied to form primary structure of poly gate. Finally, both gate etch anneal and sidewall rapid thermal oxidation are used to form the poly gate structure completely. The essential point of the method is that the metal silicide is annealed just when it is formed, such that there is no phase transition of metal silicide will occur while any further treatment of the poly gate. By the way, surface extrusion of poly gate is fundamental prevented.
摘要翻译：公开了一种用于形成多晶硅栅极结构的方法。该方法包括在衬底上形成电介质层，然后在电介质层上形成多晶硅层。然后在多晶硅层上形成金属硅化物层，并且完全完成金属硅化物的形成之后，实施退火工艺以诱导金属硅化物层的相变。之后，在金属硅化物层上形成钝化层，然后应用标准光刻法形成多晶硅的一级结构。最后，门蚀刻退火和侧壁快速热氧化都被用来完全形成多晶硅结构。该方法的要点是金属硅化物刚刚形成时退火，使得在多晶硅栅极的任何进一步处理期间不会发生金属硅化物的相变。顺便提一句，防止了多门的表面挤压。

74. 发明授权

US6153466A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US6153466A
公开(公告)日：2000-11-28
申请号：US96349
申请日：1998-06-12
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-SI on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新开始沉积，以在电极的表面上提供第二层HSG-SI。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

75. 发明授权

US6037206A Method of fabricating a capacitor of a dynamic random access memory 失效
标题翻译：制造动态随机存取存储器的电容器的方法
公开(公告)号：US6037206A
公开(公告)日：2000-03-14
申请号：US080116
申请日：1998-05-15
申请人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
发明人： Kuo-Tai Huang , Hsi-Ta Chuang , Tri-Rung Yew
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for fabricating a capacitor of a DRAM includes a lower conductive layer of the capacitor is formed over a substrate and is electrically coupled to an interchangeable source/drain region through a contact window penetrating an insulating layer. Then performing etching process on the lower conductive layer so as to form a fence-like plate with a higher height than a thickness of the lower conductive layer and adhere to the lower conductive layer. Next a media conductive layer is formed over the lower conductive layer and the fence-like plate. Then the technology of etching back is utilized to round the sharp area on the tip of the fence-like plate. The lower conductive layer and the media conductive layer are electrically coupled together as a lower electrode. Then, a dielectric thin film is formed over the media conductive layer and an upper electrode is formed over the dielectric thin film. Therefore, a MIM capacitor according to the preferred embodiment of the invention is formed.
摘要翻译：一种用于制造DRAM电容器的方法包括：电容器的下导电层形成在衬底上，并通过穿透绝缘层的接触窗电耦合到可互换的源/漏区。然后对下导电层进行蚀刻处理，以形成具有比下导电层的厚度高的高度的栅栏状的板，并粘附到下导电层。接下来，在下导电层和栅栏状板上形成介质导电层。然后，利用蚀刻技术来围绕栅栏状板的尖端上的尖锐区域。下导电层和介质导电层作为下电极电耦合在一起。然后，在介质导电层上形成电介质薄膜，在电介质薄膜上方形成上电极。因此，形成根据本发明的优选实施例的MIM电容器。

76. 发明授权

US5981395A Method of fabricating an unlanded metal via of multi-level interconnection 失效
标题翻译：制造多层互连的无衬金属通孔的方法
公开(公告)号：US5981395A
公开(公告)日：1999-11-09
申请号：US994157
申请日：1997-12-19
申请人： Yimin Huang , Tri-Rung Yew
发明人： Yimin Huang , Tri-Rung Yew
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/76897
摘要： A method of fabricating an unlanded metal via of multi-level interconnection. The method is characterized by utilizing damascene scheme to form a metal wiring layer so that the processes are simplified. Moreover, by this method of the invention, a problem of difficulty in filling dielectric material between the metal wiring lines can be avoided and the metal layer does not have to be etched prior to filling the dielectric material. Further more, an etching stop layer is formed over the first inter-metal dielectric layer to avoid overetching during the formation of metal via, which therefore avoid short circuit. Forming the metal wiring lines by damascene scheme allows the etching stop layer to be easily formed over the first dielectric layer, without over etching the metal via.
摘要翻译：一种制造多层互连的无衬金属通孔的方法。该方法的特征在于利用镶嵌方案形成金属布线层，从而简化了工艺。此外，通过本发明的这种方法，可避免难以在金属布线之间填充介电材料的问题，并且在填充电介质材料之前不必对金属层进行蚀刻。此外，在第一金属间电介质层上形成蚀刻停止层，以避免在形成金属通孔期间的过蚀刻，从而避免短路。通过镶嵌方案形成金属布线允许蚀刻停止层容易地形成在第一介电层上，而不会过度蚀刻金属通孔。

77. 发明授权

US5976931A Method for increasing capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US5976931A
公开(公告)日：1999-11-02
申请号：US775813
申请日：1996-12-31
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/84
摘要： The capacitor of a DRAM cell is formed by depositing a layer of doped polysilicon, patterning the layer of doped polysilicon to define the extent of the capacitor's lower electrode and then depositing a first layer of hemispherical-grained silicon (HSG-Si) on the layer of doped polysilicon. Growth of the first layer of HSG-Si is interrupted and then a second layer of HSG-Si is grown. In one aspect, growth of the first layer of HSG-Si may be interrupted by either cooling the deposition substrate or stopping deposition for a period of time and then reinitiating deposition to provide a second layer of HSG-Si on the surface of the electrode. The interruption of the growth of the first layer, whether by cooling or by delay, is sufficient if the reinitiated growth initiates in a manner that is independent of the first process; i.e., the second layer of HSG-Si grows independently. In a different aspect of the invention, growth of the first layer may be interrupted by removing the electrode from the deposition system and performing an etch back operation. After the etch back operation, the electrode is reintroduced to the deposition system and a second layer of HSG-Si is grown on the etched surface. This textured silicon structure forms the lower electrode of the DRAM capacitor.
摘要翻译：通过沉积掺杂多晶硅层来形成DRAM单元的电容器，图案化掺杂多晶硅层以限定电容器的下电极的范围，然后在层上沉积第一层半球状硅（HSG-Si）的掺杂多晶硅。 HSG-Si的第一层的生长被中断，然后生长第二层HSG-Si。在一个方面，HSG-Si的第一层的生长可以通过冷却沉积衬底或停止沉积一段时间而中断，然后重新沉积以在电极的表面上提供第二层HSG-Si。如果重新开始的增长以独立于第一过程的方式发起，则第一层的增长中断，无论是通过冷却还是延迟，都是足够的; 即第二层HSG-Si独立生长。在本发明的另一方面，可以通过从沉积系统中去除电极并执行回蚀作业来中断第一层的生长。在回蚀作业之后，将电极重新引入沉积系统，并在蚀刻的表面上生长第二层HSG-Si。该纹理硅结构形成DRAM电容器的下电极。

78. 发明授权

US5930618A Method of Making High-K Dielectrics for embedded DRAMS 失效
标题翻译：用于嵌入式DRAMS制备高K电介质的方法
公开(公告)号：US5930618A
公开(公告)日：1999-07-27
申请号：US943670
申请日：1997-10-03
申请人： Shih-Wei Sun , Tri-Rung Yew
发明人： Shih-Wei Sun , Tri-Rung Yew
IPC分类号： H01L21/8242
CPC分类号： H01L27/10844 , H01L27/10852
摘要： An integrated circuit device having both an array of logic circuits and embedded DRAM circuits is provided using a process that avoids some of the most significant processing challenges for embedded DRAM integration. Transfer FETs and wiring lines are provided for the embedded DRAM circuits and FETs are provided for the logic portions of the device. A thin, conformal oxide layer is provided over the surface of the device to cover the transfer FETs and the logic FETs to protect portions of the device during formation of the charge storage capacitors. A mask is provided having openings over the appropriate source/drain regions of the transfer FETs and the oxide layer is etched. A planar or substantially planar lower capacitor electrode is defined by providing and patterning a first layer of doped polysilicon over the thin protective oxide layer in contact with the desired source/drain regions of the transfer FETs. Tantalum pentoxide or barium strantium titanate might be used as the capacitor dielectric to provide the needed capacitance for the cells of the embedded DRAM array. An upper capacitor electrode is provided and the protective oxide layer is removed from the logic circuits. Because the protective oxide layer is thinner and more uniform than is conventional, it is easier to perform this etching step without damaging the FETs of the logic circuit. A conventional salicide process can then be used to complete formation of the FETs of the logic circuits of the device.
摘要翻译：具有逻辑电路阵列和嵌入式DRAM电路的集成电路器件使用避免嵌入式DRAM集成的一些最重要的处理挑战的过程来提供。为嵌入式DRAM电路提供转移FET和布线，并为器件的逻辑部分提供FET。在器件的表面上提供薄的共形氧化物层以覆盖传输FET和逻辑FET，以在形成电荷存储电容器期间保护器件的部分。提供了在转移FET的适当源极/漏极区域上具有开口的掩模，并且蚀刻氧化物层。通过在与传送FET的所需源/漏区接触的薄保护氧化物层上提供和图案化第一掺杂多晶硅层来限定平面或基本平坦的下电容器电极。可以使用五氧化二钽或钛酸钡钛酸盐作为电容器电介质，为嵌入式DRAM阵列的电池提供所需的电容。提供上电容器电极，并且从逻辑电路中去除保护氧化物层。由于保护性氧化物层比现有技术更薄且更均匀，因此在不破坏逻辑电路的FET的情况下更容易进行该蚀刻工序。然后可以使用常规的自对准硅化物工艺来完成器件的逻辑电路的FET的形成。

79. 发明授权

US5869368A Method to increase capacitance 失效
标题翻译：增加电容的方法
公开(公告)号：US5869368A
公开(公告)日：1999-02-09
申请号：US934785
申请日：1997-09-22
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40 , H01L28/92
摘要： A high capacitance charge storage capacitor for a DRAM has a lower electrode in contact with one source/drain region of a transfer FET. The lower capacitor electrode includes a first layer of polysilicon deposited over part of the transfer FET and in contact with the source/drain region of the transfer FET. An oxide layer is deposited over the first polysilicon layer and then a sparse layer of hemispherical grained polysilicon is deposited on the surface of the oxide layer. The sparse layer of hemispherical grained polysilicon has grains on the order of approximately 100 nanometers across that are separated on the average by approximately 100 nanometers. The layer of oxide is etched using the sparse grains of hemispherical grained polysilicon as a mask, with the etch process stopping on the surface of the first layer of polysilicon. A second layer of polysilicon is deposited over the remaining grains of hemispherical grained polysilicon and over the column-shaped portions of the oxide layer left by the etching stop. A capacitor dielectric is formed over the second layer of polysilicon and then an upper capacitor electrode is provided.
摘要翻译：用于DRAM的高电容电容存储电容器具有与转移FET的一个源极/漏极区域接触的下部电极。下部电容器电极包括沉积在转移FET的一部分上并与转移FET的源极/漏极区域接触的第一多晶硅层。在第一多晶硅层上沉积氧化物层，然后在氧化物层的表面上沉积半球状晶粒多晶硅的稀疏层。半球状粒状多晶硅的稀疏层具有约100纳米级的晶粒，平均分离约100纳米。使用半球状粒状多晶硅的稀疏晶粒作为掩模蚀刻氧化物层，其中蚀刻工艺停止在第一层多晶硅的表面上。第二层多晶硅沉积在半球状晶粒多晶硅的剩余晶粒之上，并在氧化物层的残留在蚀刻停止点的柱状部分之上。在第二多晶硅层上形成电容器电介质，然后提供上电容器电极。

80. 发明授权

US5753559A Method for growing hemispherical grain silicon 失效
标题翻译：生长半球状硅的方法
公开(公告)号：US5753559A
公开(公告)日：1998-05-19
申请号：US727919
申请日：1996-10-09
申请人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
发明人： Tri-Rung Yew , Water Lur , Shih-Wei Sun
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/84
摘要： Hemispherical-grained silicon (HSG-Si) is grown on polysilicon by plasma deposition. A wider range of substrate deposition temperatures can be used in the plasma deposition of HSG-Si than can be maintained in the low pressure chemical vapor deposition (LPCVD) of HSG-Si. The plasma deposition of HSG-Si can be performed in an electron cyclotron resonance chemical vapor deposition (ECR-CVD) system at input power levels ranging from 100-1500 W, at total pressures between 5-60 mTorr, and at substrate temperatures ranging from 200.degree.-500.degree. C. A mixture of silane and hydrogen gases at a dilution ratio of silane within the silane and hydrogen gas mixture H.sub.2 /(SiH.sub.4 +H.sub.2) between about 70-99% may be used in the ECR-CVD system. The polysilicon surface is cleaned of native oxides prior to plasma deposition of HSG-Si.
摘要翻译：通过等离子体沉积在半导体上生长半球状硅（HSG-Si）。可以在HSG-Si的低压化学气相沉积（LPCVD）中保持HSG-Si的等离子体沉积中使用更宽范围的衬底沉积温度。 HSG-Si的等离子体沉积可以在电子回旋共振化学气相沉积（ECR-CVD）系统中进行，输入功率水平范围为100-1500W，总压力为5-60mTorr，基底温度为 200°-500℃。在ECR-CVD系统中可以使用在硅烷内的硅烷和氢气混合物H 2 /（SiH 4 + H 2）之间约70-99％的稀释比例的硅烷和氢气的混合物。在等离子体沉积HSG-Si之前，多晶硅表面被清除了天然氧化物。

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