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1. 发明授权

US06221746B1 Method for forming a poly gate structure 有权
标题翻译：多栅结构的形成方法
公开(公告)号：US06221746B1
公开(公告)日：2001-04-24
申请号：US09223010
申请日：1998-12-30
申请人： Michael WC Huang , Tri-Rung Yew
发明人： Michael WC Huang , Tri-Rung Yew
IPC分类号： H01L214763
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/28176 , H01L21/32105 , H01L21/32136
摘要： A method for forming a poly gate structure is disclosed. The method comprises forming a dielectric layer on a substrate and then forming a polysilicon layer on the dielectric layer. A metal silicide layer is then formed on the polysilicon layer and, just after formation of metal silicide is accomplished completely, an annealing process is practiced to induce phase transformation of metal silicide layer. Afterwards, a passivation layer is formed over the metal silicide layer, and then a standard photolithography method is applied to form primary structure of poly gate. Finally, both gate etch anneal and sidewall rapid thermal oxidation are used to form the poly gate structure completely. The essential point of the method is that the metal silicide is annealed just when it is formed, such that there is no phase transition of metal silicide will occur while any further treatment of the poly gate. By the way, surface extrusion of poly gate is fundamental prevented.
摘要翻译：公开了一种用于形成多晶硅栅极结构的方法。该方法包括在衬底上形成电介质层，然后在电介质层上形成多晶硅层。然后在多晶硅层上形成金属硅化物层，并且完全完成金属硅化物的形成之后，实施退火工艺以诱导金属硅化物层的相变。之后，在金属硅化物层上形成钝化层，然后应用标准光刻法形成多晶硅的一级结构。最后，门蚀刻退火和侧壁快速热氧化都被用来完全形成多晶硅结构。该方法的要点是金属硅化物刚刚形成时退火，使得在多晶硅栅极的任何进一步处理期间不会发生金属硅化物的相变。顺便提一句，防止了多门的表面挤压。

2. 发明授权

US06249138B1 Method for testing leakage current caused self-aligned silicide 有权
标题翻译：泄漏电流测试方法引起自对准硅化物
公开(公告)号：US06249138B1
公开(公告)日：2001-06-19
申请号：US09447846
申请日：1999-11-23
申请人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
发明人： Michael WC Huang , Gwo-Shii Yang , Hsiao-Ling Lu , Wen-Yi Hsieh
IPC分类号： G01R3126
CPC分类号： G01R31/2648
摘要： A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.
摘要翻译：描述了由自对准硅化物工艺引起的漏电流的测试方法。本发明使用不同的测试结构来监测由自对准硅化物工艺引起的漏电流的程度和原因。在监视对没有LDD区域的金属氧化物半导体晶体管进行的自对准硅化物处理的同时，除了考虑从金属硅化物层发生到结以及在金属硅化物层的边缘处发生的漏电流之外，本发明进一步考虑在金属硅化物层的角落处的漏电流。对于具有LDD区域的金属氧化物半导体晶体管，本发明还考虑了从金属硅化物层到LDD区域的漏电流。本发明监测金属硅化物层的角落处的漏电流。

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