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71. 发明申请

US20060001057A1 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US20060001057A1
公开(公告)日：2006-01-05
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/80 , H01L21/338
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译：导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

72. 发明授权

US06573562B2 Semiconductor component and method of operation 有权
标题翻译：半导体元件及其操作方法
公开(公告)号：US06573562B2
公开(公告)日：2003-06-03
申请号：US10004186
申请日：2001-10-31
申请人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
发明人： Vijay Parthasarathy , Ronghua Zhu , Vishnu K. Khemka , Amitava Bose
IPC分类号： H01L2976
CPC分类号： H03K17/08 , H01L21/761 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0676 , H01L27/0814 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.
摘要翻译：半导体元件包括具有第一导电类型的第一和第二部分（111,112）的半导体衬底（110），至少部分地位于半导体衬底中的晶体管（120）和开关电路（150,350,650 ，850）。晶体管包括（i）半导体衬底的第一部分中的第一掺杂区域，并具有第一导电类型（ii）端子，其包括具有第二导电类型并位于半导体的第一部分中的第二掺杂区域衬底并且在第一掺杂区域上方，以及（iii）具有第二导电类型并且位于半导体衬底的第一部分下方并位于半导体衬底的第二部分之下的第三掺杂区域。开关电路电耦合到第三掺杂区域以调节第三掺杂区域的偏置。

73. 发明授权

US06528849B1 Dual-gate resurf superjunction lateral DMOSFET 失效
标题翻译：双栅极复合超导型DMOSFET
公开(公告)号：US06528849B1
公开(公告)日：2003-03-04
申请号：US09652813
申请日：2000-08-31
申请人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu K. Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L2978
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/7393 , H01L29/7831
摘要： A MOSFET includes a source region, a first channel region proximate to the source region, a first gate region adjacent to the first base region, a drain region, a second channel region proximate to the drain region, and a second gate region adjacent to the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate region with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate region with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region includes a set of alternating columns, each of which is also coupled between the first base region and the second base region. The set of alternating columns includes a plurality of columns doped with N− type impurities alternating with a plurality columns doped with P− type impurities.
摘要翻译： MOSFET包括源极区域，靠近源极区域的第一沟道区域，与第一基极区域相邻的第一栅极区域，漏极区域，靠近漏极区域的第二沟道区域以及与漏极区域相邻的第二栅极区域第二通道区域。根据相对于源区域的至少第一部分施加到第一栅极区域的第一电压，在第一沟道区域内形成第一沟道，并且第二沟道形成在第二沟道区内，依赖于相对于漏极区域的至少第二部分施加到第二栅极区域的第二电压。 MOSFET还包括耦合在第一沟道区域和第二沟道区域之间的漂移区域，其中漂移区域包括一组交替的列，其中每一个也耦合在第一基极区域和第二基极区域之间。这组交替的列包括掺杂有多个掺杂有P-型杂质的列的N型杂质的多个列。

74. 发明授权

US08823093B2 High-voltage transistor structure with reduced gate capacitance 有权
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US08823093B2
公开(公告)日：2014-09-02
申请号：US13532583
申请日：2012-06-25
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

75. 发明授权

US08765609B2 Deposit/etch for tapered oxide 有权
标题翻译：沉积/蚀刻锥形氧化物
公开(公告)号：US08765609B2
公开(公告)日：2014-07-01
申请号：US13558218
申请日：2012-07-25
申请人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
发明人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
IPC分类号： H01L21/311
CPC分类号： H01L29/407 , H01L21/76224
摘要： A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
摘要翻译：公开了一种用于制造用于高压半导体器件的锥形场板电介质的工艺。该方法可以包括沉积氧化物薄层，沉积多晶硅硬掩模，沉积抗蚀剂层和蚀刻沟槽区域，执行深硅沟槽蚀刻和剥离抗蚀剂层。该方法还可以包括沉积氧化物层和各向异性蚀刻氧化物以在沟槽内形成锥形壁的重复步骤。该方法还可以包括沉积多晶硅并执行进一步的处理以形成半导体器件。

76. 发明申请

US20130281839A1 VISUALIZATION OF CATHETER OF THREE-DIMENSIONAL ULTRASOUND 有权
标题翻译：三维超声波导管的可视化
公开(公告)号：US20130281839A1
公开(公告)日：2013-10-24
申请号：US13997800
申请日：2012-01-10
申请人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
发明人： Pingkun Yan , Vijay Parthasarathy , Robert Manzke , Ameet Kumar Jain
IPC分类号： A61B19/00
CPC分类号： A61B34/20 , A61B6/12 , A61B8/0883 , A61B8/466 , A61B8/483
摘要： An image-guided system employs an X-ray imaging device (20) for generating one or more X-ray images (25, 26) illustrating a tool (41) within an anatomical region (40) and an ultrasound imaging device (30) for generating an ultrasound image (33) illustrating the tool (41) within the anatomical region (40). The image-guided system further employs a tool tracking device (50) for visually tracking the tool (41) within the anatomical region (40). In operation, the tool tracking device (50) localizes a portion of the tool (41) as located within the ultrasound image (33) responsive to an identification of the portion of the tool (41) as located within the X-ray image(s) (25, 26), and executes an image segmentation of an entirety of the tool (41) as located within the ultrasound image (33) relative to a localization of the portion of the tool (41) as located within the ultrasound image (33).
摘要翻译：图像引导系统采用X射线成像装置（20），用于产生示出解剖区域（40）内的工具（41）和超声成像装置（30）的一个或多个X射线图像（25,26）用于产生示出所述解剖区域（40）内的所述工具（41）的超声图像（33）。图像引导系统还采用用于在解剖区域（40）内目视跟踪工具（41）的工具跟踪装置（50）。在操作中，工具跟踪装置（50）响应于位于X射线图像内的工具（41）的部分的识别，使位于超声波图像（33）内的工具（41）的一部分定位 s）（25,26），并且相对于位于超声波图像内的工具（41）的部分的定位，执行位于超声波图像（33）内的整个工具（41）的图像分割（33）。

77. 发明授权

US08426915B2 Power integrated circuit device with incorporated sense FET 有权
标题翻译：功率集成电路器件，内置有感应FET
公开(公告)号：US08426915B2
公开(公告)日：2013-04-23
申请号：US13532507
申请日：2012-06-25
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L21/66
CPC分类号： H01L29/772 , H01L27/0629 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/7835
摘要： In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.
摘要翻译：在一个实施例中，功率集成电路器件包括形成在高电阻率衬底上的主横向高电压场效应晶体管（HVFET）和相邻定位的横向感测FET。感测电阻器形成在设置在HVFET和感测FET之间的衬底区域中的阱区中。寄生衬底电阻器形成为与HVFET的源极区域和感测FET之间的感测电阻器并联电连接。两个晶体管器件共享共同的漏极和栅电极。当主横向HVFET和感测FET处于导通状态时，在与流过横向HVFET的第一电流成比例的第二源极金属层处产生电压电位。

78. 发明授权

US08395207B2 High-voltage vertical transistor with a varied width silicon pillar 有权
标题翻译：具有不同宽度硅柱的高压立式晶体管
公开(公告)号：US08395207B2
公开(公告)日：2013-03-12
申请号：US13134504
申请日：2011-06-08
申请人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
发明人： Vijay Parthasarathy , Sujit Banerjee , Lin Zhu
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L29/0657 , H01L29/0696 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions.
摘要翻译：在一个实施例中，垂直HVFET包括半导体材料的柱状半导体材料的柱，其布置成具有至少两个具有第一宽度的至少两个基本上平行且基本上线性的圆角部分的环形布局，以及至少两个圆形部分，具有比第一宽度窄的第二宽度，第一导电类型的源极区域设置在柱的顶表面处或附近，并且第二导电类型的主体区域设置在源极区域下方的柱中。第一和第二电介质区域分别设置在柱的相对侧上，第一介质区域被柱侧向包围，第二介质区域横向围绕柱。第一和第二场板分别设置在第一和第二电介质区域中。

79. 发明申请

US20120306012A1 Power Integrated Circuit Device With Incorporated Sense FET 有权
标题翻译：具有并入感测FET的功率集成电路器件
公开(公告)号：US20120306012A1
公开(公告)日：2012-12-06
申请号：US13532507
申请日：2012-06-25
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L27/088
CPC分类号： H01L29/772 , H01L27/0629 , H01L27/088 , H01L29/0692 , H01L29/0696 , H01L29/7835
摘要： In one embodiment, a power integrated circuit device includes a main lateral high-voltage field-effect transistor (HVFET) and an adjacently-located lateral sense FET, both of which are formed on a high-resistivity substrate. A sense resistor is formed in a well region disposed in an area of the substrate between the HVFET and the sense FET. A parasitic substrate resistor is formed in parallel electrical connection with the sense resistor between the source regions of the HVFET and the sense FET. Both transistor devices share common drain and gate electrodes. When the main lateral HVFET and the sense FET are in an on-state, a voltage potential is produced at the second source metal layer that is proportional to a first current flowing through the lateral HVFET.
摘要翻译：在一个实施例中，功率集成电路器件包括形成在高电阻率衬底上的主横向高电压场效应晶体管（HVFET）和相邻定位的横向感测FET。感测电阻器形成在设置在HVFET和感测FET之间的衬底区域中的阱区中。寄生衬底电阻器形成为与HVFET的源极区域和感测FET之间的感测电阻器并联电连接。两个晶体管器件共享共同的漏极和栅电极。当主横向HVFET和感测FET处于导通状态时，在与流过横向HVFET的第一电流成比例的第二源极金属层处产生电压电位。

80. 发明授权

US08247287B2 Method of fabricating a deep trench insulated gate bipolar transistor 失效
标题翻译：制造深沟槽绝缘栅双极晶体管的方法
公开(公告)号：US08247287B2
公开(公告)日：2012-08-21
申请号：US13373210
申请日：2011-11-08
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L21/8249
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
摘要翻译：在一个实施例中，一种方法包括在相反导电类型的衬底上形成外延层，该外延层被缓冲层隔开，该缓冲层的垂直方向上的缓冲层的掺杂浓度基本上是恒定的。至少在缓冲层中，从外延层的顶表面在外延层中形成一对间隔开的沟槽。在第一和第二侧壁部分上的沟槽中形成电介质材料。源极/集电极和主体区域形成在外延层的顶部，体区域将柱的源极/集电极区域与从体区域延伸到缓冲层的外延层的漂移区域分离。然后在与身体区域相邻并与其绝缘的每个沟槽中形成绝缘门构件。

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