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1. 发明授权

US08765609B2 Deposit/etch for tapered oxide 有权
标题翻译：沉积/蚀刻锥形氧化物
公开(公告)号：US08765609B2
公开(公告)日：2014-07-01
申请号：US13558218
申请日：2012-07-25
申请人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
发明人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
IPC分类号： H01L21/311
CPC分类号： H01L29/407 , H01L21/76224
摘要： A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
摘要翻译：公开了一种用于制造用于高压半导体器件的锥形场板电介质的工艺。该方法可以包括沉积氧化物薄层，沉积多晶硅硬掩模，沉积抗蚀剂层和蚀刻沟槽区域，执行深硅沟槽蚀刻和剥离抗蚀剂层。该方法还可以包括沉积氧化物层和各向异性蚀刻氧化物以在沟槽内形成锥形壁的重复步骤。该方法还可以包括沉积多晶硅并执行进一步的处理以形成半导体器件。

2. 发明申请

US20140030868A1 DEPOSIT/ETCH FOR TAPERED OXIDE 有权
标题翻译：沉积氧化物的沉积/蚀刻
公开(公告)号：US20140030868A1
公开(公告)日：2014-01-30
申请号：US13558218
申请日：2012-07-25
申请人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
发明人： Vijay Parthasarathy , Sujit Banerjee , Wayne B. Grabowski
IPC分类号： H01L21/76
CPC分类号： H01L29/407 , H01L21/76224
摘要： A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
摘要翻译：公开了一种用于制造用于高压半导体器件的锥形场板电介质的工艺。该方法可以包括沉积氧化物薄层，沉积多晶硅硬掩模，沉积抗蚀剂层和蚀刻沟槽区域，执行深硅沟槽蚀刻和剥离抗蚀剂层。该方法还可以包括沉积氧化物层和各向异性蚀刻氧化物以在沟槽内形成锥形壁的重复步骤。该方法还可以包括沉积多晶硅并执行进一步的处理以形成半导体器件。

3. 发明申请

US20120273885A1 High-Voltage Transistor Structure with Reduced Gate Capacitance 有权
标题翻译：具有降低栅极电容的高压晶体管结构
公开(公告)号：US20120273885A1
公开(公告)日：2012-11-01
申请号：US13532583
申请日：2012-06-25
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0634 , H01L29/0692 , H01L29/0882 , H01L29/42368
摘要： In one embodiment, a high voltage field-effect transistor (HVFET) includes a field oxide layer that covers a first well region, the field oxide layer having a first thickness and extending in a second lateral direction from a drain region to near a second well region. A gate oxide covers a channel region and has a second dimension in a first lateral direction. A gate extends in the second lateral direction from the source region to over a portion of the field oxide layer, the gate being insulated from the channel region by the gate oxide, the gate extending in the first lateral dimension over an inactive area of the HVFET beyond the second dimension of the gate oxide, the gate being insulated from the first and second well regions over the inactive area by the field oxide layer.
摘要翻译：在一个实施例中，高电压场效应晶体管（HVFET）包括覆盖第一阱区的场氧化物层，所述场氧化物层具有第一厚度并且在第二横向方向上从漏极区延伸到接近第二阱地区。栅极氧化物覆盖沟道区域并且具有在第一横向方向上的第二尺寸。栅极在第二横向方向上从源极区域延伸到场氧化物层的一部分，栅极通过栅极氧化物与沟道区域绝缘，栅极在第一横向尺寸上延伸超过HVFET的非有效区域超过栅极氧化物的第二维度，栅极通过场氧化物层与无源区域上的第一和第二阱区绝缘。

4. 发明申请

US20120146105A1 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US20120146105A1
公开(公告)日：2012-06-14
申请号：US13385264
申请日：2012-02-10
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L27/06
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，在JFET的端子处提供的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。

5. 发明申请

US20120061755A1 Checkerboarded high-voltage vertical transistor layout 失效
标题翻译：棋盘式高压立式晶体管布局
公开(公告)号：US20120061755A1
公开(公告)日：2012-03-15
申请号：US13199792
申请日：2011-09-09
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/78
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。第一和第二电介质区域设置在柱的相对侧上。第一和第二场板分别设置在第一和第二电介质区域中。邻接第一和第二部分的晶体管段的外场板被分离或部分合并。

6. 发明申请

US20110140166A1 Method of fabricating a deep trench insulated gate bipolar transistor 失效
公开(公告)号：US20110140166A1
公开(公告)日：2011-06-16
申请号：US12930626
申请日：2011-01-11
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.

7. 发明申请

US20110042726A1 High-voltage transistor device with integrated resistor 有权
标题翻译：具有集成电阻的高压晶体管器件
公开(公告)号：US20110042726A1
公开(公告)日：2011-02-24
申请号：US12583426
申请日：2009-08-20
申请人： Sujit Banerjee , Vijay Parthasarathy
发明人： Sujit Banerjee , Vijay Parthasarathy
IPC分类号： H01L29/80 , H01L27/105
CPC分类号： H01L29/808 , H01L27/0629 , H01L28/20 , H01L29/0634 , H01L29/1058 , H01L29/1066
摘要： A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：高压器件结构包括耦合到抽头晶体管的电阻器，其包括JFET，其中当外部电压小于钳位电压时，JFET端子处的电压基本上与外部电压成比例的JFET。当外部电压大于夹断电压时，端子处提供的电压基本上恒定。当外部电压大于夹断电压时，电阻器的一端基本上处于外部电压。当外部电压为负时，电阻限制注入基板的电流。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

8. 发明授权

US07859037B2 Checkerboarded high-voltage vertical transistor layout 有权
标题翻译：棋盘式高压立式晶体管布局
公开(公告)号：US07859037B2
公开(公告)日：2010-12-28
申请号：US11707418
申请日：2007-02-16
申请人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
发明人： Vijay Parthasarathy , Sujit Banerjee , Martin H. Manley
IPC分类号： H01L29/94 , H01L27/108
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译：在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。这些部分基本上跨越半导体管芯排列成行和列。一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在第二方向，第一方向基本上与第二方向正交。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。

9. 发明申请

US20100155831A1 Deep trench insulated gate bipolar transistor 审中-公开
标题翻译：深沟槽绝缘栅双极晶体管
公开(公告)号：US20100155831A1
公开(公告)日：2010-06-24
申请号：US12317307
申请日：2008-12-20
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L29/78
CPC分类号： H01L29/7397 , H01L29/0649 , H01L29/0653 , H01L29/66348
摘要： In one embodiment, a power transistor device comprises a substrate of a first conductivity type that forms a PN junction with an overlying buffer layer of a second conductivity type. The power transistor device further includes a first region of the second conductivity type, a drift region of the second conductivity type that adjoins a top surface of the buffer layer, and a body region of the first conductivity type. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.
摘要翻译：在一个实施例中，功率晶体管器件包括与第二导电类型的上覆缓冲层形成PN结的第一导电类型的衬底。功率晶体管器件还包括第二导电类型的第一区域，与缓冲层的顶表面相邻的第二导电类型的漂移区域和第一导电类型的体区域。身体区域将第一区域与漂移区域分开。第一和第二电介质区域分别邻接漂移区域的相对的侧向侧壁部分。电介质区域至少在身体区域的正下方沿垂直方向向下延伸至少至缓冲层。控制正向传导的沟槽栅极设置在与身体区域相邻并绝缘的电介质区域的上方。

10. 发明授权

US08410548B2 Method of fabricating a deep trench insulated gate bipolar transistor 失效
标题翻译：制造深沟槽绝缘栅双极晶体管的方法
公开(公告)号：US08410548B2
公开(公告)日：2013-04-02
申请号：US13565846
申请日：2012-08-03
申请人： Vijay Parthasarathy , Sujit Banerjee
发明人： Vijay Parthasarathy , Sujit Banerjee
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/66333
摘要： In one embodiment, a method comprises forming an epitaxial layer over a substrate of an opposite conductivity type, the epitaxial layer being separated by a buffer layer having a doping concentration that is substantially constant in a vertical direction down to the buffer layer. A pair of spaced-apart trenches is formed in the epitaxial layer from a top surface of the epitaxial layer down at least into the buffer layer. A dielectric material is formed in the trenches over the first and second sidewall portions. Source/collector and body regions of are formed at the top of the epitaxial layer, the body region separating the source/collector region of the pillar from a drift region of the epitaxial layer that extends from the body region to the buffer layer. An insulated gate member is then formed in each of the trenches adjacent to and insulated from the body region.
摘要翻译：在一个实施例中，一种方法包括在相反导电类型的衬底上形成外延层，该外延层被缓冲层隔开，该缓冲层的垂直方向上的缓冲层的掺杂浓度基本上是恒定的。至少在缓冲层中，从外延层的顶表面在外延层中形成一对间隔开的沟槽。在第一和第二侧壁部分上的沟槽中形成电介质材料。源极/集电极和主体区域形成在外延层的顶部，体区域将柱的源极/集电极区域与从体区域延伸到缓冲层的外延层的漂移区域分离。然后在与身体区域相邻并与其绝缘的每个沟槽中形成绝缘门构件。

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