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71. 发明授权

US08958232B2 Method and apparatus for read assist to compensate for weak bit 有权
标题翻译：用于读取辅助补偿弱点的方法和装置
公开(公告)号：US08958232B2
公开(公告)日：2015-02-17
申请号：US13437081
申请日：2012-04-02
申请人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
发明人： Jonathan Tsung-Yung Chang , Cheng Hung Lee , Chung-Cheng Chou , Hung-Jen Liao , Bin-Hau Lo
IPC分类号： G11C17/00
CPC分类号： G11C7/12 , G11C7/067 , G11C11/412 , G11C11/419
摘要： A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.
摘要翻译：记忆辅助装置包括检测电路和补偿电路。检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

72. 发明授权

US08675439B2 Bit line voltage bias for low power memory design 有权
标题翻译：用于低功耗存储器设计的位线电压偏置
公开(公告)号：US08675439B2
公开(公告)日：2014-03-18
申请号：US13271353
申请日：2011-10-12
申请人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
发明人： Hong-Chen Cheng , Jung-Ping Yang , Chiting Cheng , Cheng-Hung Lee , Sang H. Dong , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C7/12 , G11C11/419
摘要： In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.
摘要翻译：在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和响应于控制信号的待机模式。位线偏置电路控制在处于睡眠模式时使位线浮动的电压。用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

73. 发明授权

US08576655B2 Semiconductor memories 有权
标题翻译：半导体存储器
公开(公告)号：US08576655B2
公开(公告)日：2013-11-05
申请号：US13164807
申请日：2011-06-21
申请人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
发明人： Wei Min Chan , Yen-Huei Chen , Jihi-Yu Lin , Hsien-Yu Pan , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412
摘要： A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
摘要翻译：半导体存储器包括具有形成锁存器的第一和反相器的位单元。第一和第二晶体管分别耦合到锁存器的第一和第二存储节点以及第一和第二写入位线。第一和第二晶体管中的每一个具有耦合到第一节点的相应栅极。第三和第四晶体管在第一节点处串联耦合在一起，并且设置在写入字线和第一电压源之间。第一和第二晶体管中的每一个具有耦合到第一控制线的相应栅极。第五晶体管具有耦合到第二电压源的源极，耦合到锁存器的至少一个反相器的漏极和耦合到第一节点的栅极。读端口耦合到第一读位线和锁存器的第二存储节点。

74. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

75. 发明授权

US08406075B2 Ultra-low leakage memory architecture 有权
标题翻译：超低泄漏存储器架构
公开(公告)号：US08406075B2
公开(公告)日：2013-03-26
申请号：US12694032
申请日：2010-01-26
申请人： Cheng Hung Lee , Hung-Jen Liao
发明人： Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/063
摘要： An integrated circuit structure includes an active power supply line and a data-retention power supply line. A memory macro is connected to the active power supply line and the data-retention power supply line. The memory macro includes a memory cell array and a switch. The switch is configured to switch a connection between connecting the memory cell array to the active power supply line and connecting the memory cell array to the data-retention power supply line. The data-retention power supply line is outside of the memory macro.
摘要翻译：集成电路结构包括有源电源线和数据保持电源线。存储器宏连接到有源电源线和数据保持电源线。存储器宏包括存储单元阵列和开关。该开关被配置为在将存储单元阵列连接到有源电源线之间切换连接，并将存储单元阵列连接到数据保持电源线。数据保持电源线在存储器宏之外。

76. 发明授权

US07505345B2 Circuit and method for an SRAM with two phase word line pulse 有权
标题翻译：具有两相字线脉冲的SRAM的电路和方法
公开(公告)号：US07505345B2
公开(公告)日：2009-03-17
申请号：US11811659
申请日：2007-06-11
申请人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
发明人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
IPC分类号： G11C7/02
CPC分类号： G11C11/418 , G11C8/08
摘要： A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.
摘要翻译：一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩响应于第一和第二定时电路在字线脉冲的第二相位中的电压。第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。因此，SRAM的工作裕度得到改善。提供了使用两相字线脉冲来操作SRAM的方法。

77. 发明授权

US07436696B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07436696B2
公开(公告)日：2008-10-14
申请号：US11582116
申请日：2006-10-17
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.
摘要翻译：读优选SRAM单元包括具有第一驱动电流的上拉MOS器件，耦合到上拉MOS器件的下拉MOS器件，具有第二驱动电流的下拉MOS器件，栅极MOS器件具有耦合到上拉MOS器件和下拉MOS器件的第三驱动电流。第一驱动电流和第三驱动电流优选地具有在约0.5和约1之间的α比率。第二驱动电流和第三驱动电流优选具有在约1.45和5之间的β比率。

78. 发明授权

US07394637B2 Sense amplifier with leakage compensation for electrical fuses 有权
标题翻译：带有漏电补偿功能的感应放大器
公开(公告)号：US07394637B2
公开(公告)日：2008-07-01
申请号：US11304174
申请日：2005-12-15
申请人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
发明人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
IPC分类号： H02H5/04
CPC分类号： G11C17/18
摘要： A sense amplifier for detecting a logic state of a selected electrical fuse cell among a number of unselected electrical fuse cells includes a bias module coupled to a power supply for generating a first current, and a tracking module coupled to the bias module for generating a second current. A current supplier is coupled to the bias module and the tracking module for generating a third current substantially equal to a sum of the first and second currents scaled by a predetermined factor, the third current being diverted into a first sub-current flowing through the selected electrical fuse cell and a second sub-current leaking through the unselected electrical fuse cells. The tracking module is so configured that the second current scaled by the predetermined factor is substantially equal to the second sub-current, thereby avoiding the first sub-current to be reduced by the second sub-current.
摘要翻译：用于检测多个未选择的电熔丝单元中的所选择的电熔丝单元的逻辑状态的读出放大器包括耦合到电源的用于产生第一电流的偏置模块，以及耦合到偏置模块的跟踪模块，用于产生第二当前。当前供应商耦合到偏置模块和跟踪模块，用于产生基本上等于由预定因子缩放的第一和第二电流之和的第三电流，第三电流被转移到流过所选择的第一电流的第一子电流电熔丝单元和第二子电流通过未选择的电熔丝单元泄漏。跟踪模块被配置为使得按预定因子缩放的第二电流基本上等于第二子电流，从而避免第一子电流被第二子电流减小。

79. 发明申请

US20080112212A1 Circuits for improving read and write margins in multi-port SRAMS 有权
标题翻译：用于提高多端口SRAMS中读写余量的电路
公开(公告)号：US20080112212A1
公开(公告)日：2008-05-15
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.
摘要翻译：公开了一种用于写入耦合到互补的第一和第二位线（BL）的SRAM单元的系统和方法，所述方法包括断言将SRAM单元选择为第一正电压的字线（WL），提供第二正电压在第一BL处，在第二BL处提供第一负电压，并且将不选择SRAM单元的多个WL确定为第二负电压，其中增加了SRAM单元的写入裕度。

80. 发明申请

US20080062605A1 Repair circuitry with an enhanced ESD protection device 有权
标题翻译：具有增强型ESD保护装置的修复电路
公开(公告)号：US20080062605A1
公开(公告)日：2008-03-13
申请号：US11512830
申请日：2006-08-30
申请人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
发明人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
IPC分类号： H02H5/04
CPC分类号： G11C29/02 , G11C17/18 , G11C29/027
摘要： A repair circuitry consisting of at least one electrical fuse forming part of a conduction path between a positive voltage supply (Vq) pad and a complimentary lower voltage supply source (Vss). The repair circuitry includes at least one switching device and at least one control circuitry. The at least one switching device has a control terminal and is coupled between the Vq pad and the at least one electrical fuse. The at least one control circuitry is coupled to the control terminal and the Vq pad respectively. Upon an application of a positive high voltage to the Vq pad, the control circuitry delays the turned-on state of the switching device for a predetermined period of time, thereby blocking stray currents occurred during ESD events. Consequently, the repair circuitry can prevent the at least one electrical fuse from being mistakenly programmed.
摘要翻译：修复电路由至少一个电熔丝构成，形成正电压源（Vq）焊盘和互补的低电压源（Vss）之间的传导路径的一部分。修复电路包括至少一个开关装置和至少一个控制电路。所述至少一个开关装置具有控制端子，并且耦合在所述Vq焊盘和所述至少一个电熔丝之间。至少一个控制电路分别耦合到控制端子和Vq焊盘。当向Vq焊盘施加正高电压时，控制电路将开关器件的接通状态延迟预定的时间段，从而阻止在ESD事件期间发生的杂散电流。因此，修理电路可以防止至少一个电熔丝被错误编程。

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