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71. 发明授权

US07619911B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

72. 发明申请

US20090086551A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090086551A1
公开(公告)日：2009-04-02
申请号：US12285204
申请日：2008-09-30
申请人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
发明人： Akira Ide , Yasuhiro Takai , Riichiro Takemura , Tomonori Sekiguchi
IPC分类号： G11C7/00 , G06F11/00 , G06F11/10 , G11C8/00
CPC分类号： G11C11/4093 , G06F11/1004 , G11C7/1006 , G11C7/1012 , G11C8/12
摘要： Disclosed is a semiconductor device in which In case a data group output from a first output pin in a first word configuration is output from the first output pin and a second output pin in a second word configuration, and a data group output from a third output pin in a first word configuration is output from the third output pin and a fourth output pin in a second word configuration, the second output pin is arranged adjacent to the first output pin, and the fourth output pin is arranged adjacent to the third output pin.
摘要翻译：公开了一种半导体器件，其中如果以第一字配置从第一输出引脚输出的数据组以第二字配置从第一输出引脚和第二输出引脚输出，并且从第三输出输出数据组第一字配置中的引脚以第二字配置从第三输出引脚和第四输出引脚输出，第二输出引脚被布置为与第一输出引脚相邻，并且第四输出引脚被布置为与第三输出引脚。

73. 发明授权

US07505299B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07505299B2
公开(公告)日：2009-03-17
申请号：US11976531
申请日：2007-10-25
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/24 , G11C7/02 , G11C8/00
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

74. 发明申请

US20080175084A1 SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER CIRCUIT 有权
标题翻译：半导体存储器件和感测放大器电路
公开(公告)号：US20080175084A1
公开(公告)日：2008-07-24
申请号：US11969223
申请日：2008-01-03
申请人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
发明人： Satoru AKIYAMA , Tomonori Sekiguchi , Riichiro Takemura , Hiroaki Nakaya , Shinichi Miyatake , Yuko Watanabe
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , H01L27/10897
摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.
摘要翻译：一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或下拉电路失活。

75. 发明授权

US07372726B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07372726B2
公开(公告)日：2008-05-13
申请号：US11547616
申请日：2005-04-01
申请人： Hideyuki Matsuoka , Riichiro Takemura
发明人： Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C7/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.
摘要翻译：公开了一种使用硫属化物作为记录介质的相变存储器，其防止产生读取干扰并高速读取数据。在包括选择晶体管和硫族化物的相变存储单元阵列中，选择晶体管的衬底电位在垂直于字线的方向上被隔离。在数据记录期间，正向电流信号在衬底和连接到硫族化物的源极线之间流动，并且不使用选择晶体管。在数据读取期间，选择晶体管选择所需的单元。因此，记录电压大大高于读取电压，从而防止读取干扰的发生，并且实现高速操作。

76. 发明申请

US20080017904A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080017904A1
公开(公告)日：2008-01-24
申请号：US11773990
申请日：2007-07-06
申请人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
发明人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.
摘要翻译：提供了能够实现降低功耗，高速运行和高可靠性的DRAM。构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

77. 发明申请

US20070217254A1 Semiconductor Memory 有权
标题翻译：半导体存储器
公开(公告)号：US20070217254A1
公开(公告)日：2007-09-20
申请号：US11547616
申请日：2005-04-01
申请人： Hideyuki Matsuoka , Riichiro Takemura
发明人： Hideyuki Matsuoka , Riichiro Takemura
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.
摘要翻译：公开了一种使用硫属化物作为记录介质的相变存储器，其防止产生读取干扰并高速读取数据。在包括选择晶体管和硫族化物的相变存储单元阵列中，选择晶体管的衬底电位在垂直于字线的方向上被隔离。在数据记录期间，正向电流信号在衬底和连接到硫族化物的源极线之间流动，并且不使用选择晶体管。在数据读取期间，选择晶体管选择所需的单元。因此，记录电压大大高于读取电压，从而防止读取干扰的发生，并且实现高速操作。

78. 发明申请

US20070211544A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070211544A1
公开(公告)日：2007-09-13
申请号：US11797843
申请日：2007-05-08
申请人： Riichiro Takemura
发明人： Riichiro Takemura
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2013/0057
摘要： In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.
摘要翻译：在特别包括相变材料的半导体器件中，读出操作的可靠性提高。在相变存储器的读出操作中，要读出的位线预先充电足够低的电压，可以防止破坏性读取操作。在这种状态下，在字线被激活并且经过经过低电阻状态的存储元件充分放电的时段（首先读出）之后，在位线和读位之间执行电荷共享预充电到高电压的读出放大器的行，再次执行读出操作（第二次读出）。因此，可以在抑制读取电流的同时增加读出信号量。

79. 发明授权

US07239562B2 Semiconductor device 有权
公开(公告)号：US07239562B2
公开(公告)日：2007-07-03
申请号：US11313833
申请日：2005-12-22
申请人： Riichiro Takemura
发明人： Riichiro Takemura
IPC分类号： G11C7/10
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C2013/0054 , G11C2013/0057
摘要： In a semiconductor device particularly including a phase change material, the reliability of the read-out operation is improved. In a read-out operation of a phase change memory, a bit line to be read out is precharged in advance with a sufficiently low voltage that can prevent the destructive read operation. In this state, after a word line is activated and a period in which the voltage is sufficiently discharged via a storage element which is in a low resistance state elapses (first read out), charge sharing is performed between the bit line and a read bit line of a sense amplifier which is precharged to a high voltage, and a read-out operation is performed again (second read out). Consequently, the read-out signal amount can be increased while suppressing the read current.

80. 发明申请

US20070070716A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070070716A1
公开(公告)日：2007-03-29
申请号：US11598702
申请日：2006-11-14
申请人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Takeshi Sakata , Norikatsu Takaura , Kazuhiko Kajigaya
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/004 , G11C2213/79
摘要： There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
摘要翻译：实现了高集成度和高速度的非易失性存储器，其可以在短的操作周期时间内稳定相变存储器的操作。在写入驱动器中提供锁存器。通过写使能信号，每列循环执行相变元件的高电阻状态的改变，并且在预充电命令被输入之后执行到其低电阻状态的改变，并且同时具有去激活的预充电信号。由此，对相变电阻变为低电阻状态的存储单元的写入时间，以及从相变电阻改变为高电阻状态到读操作的写操作的周期可以延长上述存储单元，而不延长列周期时间，从而实现稳定的写操作。

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