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1. 发明申请

US20080017904A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080017904A1
公开(公告)日：2008-01-24
申请号：US11773990
申请日：2007-07-06
申请人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
发明人： Satoru AKIYAMA , Ryuta Tsuchiya , Tomonori Sekiguchi , Riichiro Takemura , Masayuki Nakamura , Yasushi Yamazaki , Shigeru Shiratake
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.
摘要翻译：提供了能够实现降低功耗，高速运行和高可靠性的DRAM。构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

2. 发明授权

US07609572B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07609572B2
公开(公告)日：2009-10-27
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

3. 发明授权

US07633833B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07633833B2
公开(公告)日：2009-12-15
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro Takemura , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

4. 发明申请

US20080239865A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080239865A1
公开(公告)日：2008-10-02
申请号：US12028788
申请日：2008-02-09
申请人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
发明人： Riichiro TAKEMURA , Tomonori Sekiguchi , Satoru Akiyama , Hiroaki Nakaya , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.
摘要翻译：根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

5. 发明申请

US20080181026A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20080181026A1
公开(公告)日：2008-07-31
申请号：US11963831
申请日：2007-12-22
申请人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
发明人： Hiroaki Nakaya , Riichiro Takemura , Satoru Akiyama , Tomonori Sekiguchi , Masayuki Nakamura , Shinichi Miyatake
IPC分类号： G11C7/08
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.
摘要翻译：在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低感觉速度增加。因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

6. 发明授权

US06538945B2 Sense amplifiers having reduced Vth deviation 有权
公开(公告)号：US06538945B2
公开(公告)日：2003-03-25
申请号：US10050561
申请日：2002-01-18
申请人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
发明人： Riichiro Takemura , Tsugio Takahashi , Masayuki Nakamura , Ryo Nagai , Norikatsu Takaura , Tomonori Sekiguchi , Shinichiro Kimura
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C11/4091 , H01L21/823807 , H01L27/092 , H01L27/10873 , H01L27/10897
摘要： Providing a semiconductor device which lessen influence of the transistor threshold voltage deviation that is one of noise elements when the sense amplifiers are amplified, and which are capable of accurately sensing and amplifying micro signals having read from the memory cells in the sense amplifiers. In a DRAM chip, P+-type gate PMOSs of P+-type polysilicon gates each having a low impurity density of channel and N+-type gate NMOSs of N+-type polysilicon gates are used in a sense amplifier cross coupling section to further increase substrate voltages of the PMOSs and to decrease substrate voltages of the NMOS. For this reason, a deviation of threshold voltage caused by channel implantation is reduced, and a small signal generated on a data line at a read operation of a low-potential memory array is accurately sensed and amplified by a sense amplifier. In addition, the threshold voltages are increased by a substrate bias effect, and a leakage current in a sense amplifier data holding state is reduced.

7. 发明授权

US09153807B2 Laminated battery and manufacturing method thereof 有权
标题翻译：层叠电池及其制造方法
公开(公告)号：US09153807B2
公开(公告)日：2015-10-06
申请号：US13266226
申请日：2010-05-14
申请人： Ryuichi Amagai , Masayuki Nakamura
发明人： Ryuichi Amagai , Masayuki Nakamura
IPC分类号： H01M2/10 , H01M2/20 , H01M2/30 , H01M2/34 , H01M10/052
CPC分类号： H01M2/1077 , H01M2/206 , H01M2/305 , H01M2/34 , H01M10/052 , Y10T29/49108
摘要： A laminated battery formed by laminating a plurality of flat cells each having an electrode tab includes: an insulating member disposed to prevent a short-circuit in the electrode tab; and a terminal connected to the electrode tab, wherein a tip end side of the terminal is supported by a support member provided on the insulating member.
摘要翻译：通过层叠多个具有电极接头的扁平电池而形成的层叠电池包括：绝缘部件，设置为防止电极接头中的短路; 以及连接到所述电极接头的端子，其中，所述端子的前端侧由设置在所述绝缘构件上的支撑构件支撑。

8. 发明授权

US08772283B2 Imidazo-oxazine compound or salt thereof 有权
标题翻译：咪唑并恶嗪化合物或其盐
公开(公告)号：US08772283B2
公开(公告)日：2014-07-08
申请号：US14004446
申请日：2012-04-05
申请人： Masayuki Nakamura , Kenji Niiyama , Kaori Kamijo , Mitsuru Ohkubo , Toshiyasu Shimomura
发明人： Masayuki Nakamura , Kenji Niiyama , Kaori Kamijo , Mitsuru Ohkubo , Toshiyasu Shimomura
IPC分类号： C07D498/04 , C07D498/14 , A61K31/5365
CPC分类号： C07D498/04 , A61K31/5365 , C07D498/14
摘要： The present invention provides an imidazooxazine compound represented by Formula (I) or a salt thereof, wherein A, B, C, and D are as defined in the specification.
摘要翻译：本发明提供由式（I）表示的咪唑并恶嗪化合物或其盐，其中A，B，C和D如说明书中所定义。

9. 发明授权

US08422263B2 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US08422263B2
公开(公告)日：2013-04-16
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

10. 再颁专利

USRE42659E1 Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed 有权
标题翻译：大容量半导体存储器，具有改进的子放大器布局，以提高速度
公开(公告)号：USRE42659E1
公开(公告)日：2011-08-30
申请号：US11759316
申请日：2007-06-07
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及指定的子公共I / O线选择性地连接的主要公共I / O。

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