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71. 发明授权

US06486080B2 Method to form zirconium oxide and hafnium oxide for high dielectric constant materials 失效
标题翻译：用于高介电常数材料形成氧化锆和氧化铪的方法
公开(公告)号：US06486080B2
公开(公告)日：2002-11-26
申请号：US09726656
申请日：2000-11-30
申请人： Simon Chooi , Wenhe Lin , Mei Sheng Zhou
发明人： Simon Chooi , Wenhe Lin , Mei Sheng Zhou
IPC分类号： H01L2131
CPC分类号： H01L21/02271 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/02189 , H01L21/31604 , H01L21/31691
摘要： A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an oxidant gas in a chemical vapor deposition chamber. The metal oxide layer may comprise hafnium oxide or zirconium oxide. The precursor may comprise metal alkoxide, metal alkoxide containing halogen, metal &bgr;-diketonate, metal fluorinated &bgr;-diketonate, metal oxoacid, metal acetate, or metal alkene. The metal oxide layer is annealed to cause densification and to complete the formation of the metal oxide dielectric layer in the manufacture of the integrated circuit device. A composite metal oxide-silicon oxide (MO2-SiO2) high dielectric constant layer may be deposited using a precursor comprising metal tetrasiloxane.
摘要翻译：已经实现了在制造集成电路器件中形成金属氧化物高介电常数层的新方法。提供基板。通过在化学气相沉积室中使前体与氧化剂气体反应而沉积在衬底上的金属氧化物层。金属氧化物层可以包括氧化铪或氧化锆。前体可以包含金属醇盐，含有卤素的金属醇盐，β-二酮金属，氟化β-二酮金属，金属氧代酸，金属乙酸盐或金属烯烃。在集成电路器件的制造中，对金属氧化物层进行退火以致致密化并完成金属氧化物介电层的形成。可以使用包含金属四硅氧烷的前体来沉积复合金属氧化物 - 氧化硅（MO2-SiO2）高介电常数层。

72. 发明授权

US06475908B1 Dual metal gate process: metals and their silicides 有权
标题翻译：双金属栅极工艺：金属及其硅化物
公开(公告)号：US06475908B1
公开(公告)日：2002-11-05
申请号：US09981415
申请日：2001-10-18
申请人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
发明人： Wenhe Lin , Mei-Sheng Zhou , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L29/66545 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/517
摘要： Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.
摘要翻译：描述形成双金属栅极CMOS晶体管的方法。半导体衬底的NMOS和PMOS有源区由隔离区隔开。金属层沉积在每个有源区域中的栅极电介质层上。将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。介电层被平坦化，从而暴露虚拟栅极。去除虚拟栅极留下栅极开口到半导体衬底。金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

73. 发明授权

US06387765B2 Method for forming an extended metal gate using a damascene process 有权
标题翻译：使用镶嵌工艺形成延伸金属浇口的方法
公开(公告)号：US06387765B2
公开(公告)日：2002-05-14
申请号：US09946982
申请日：2001-09-06
申请人： Vijai Kumar Chhagan , Yelehanka Ramachandramurthy Pradeep , Mei Sheng Zhou , Henry Gerung , Simon Chooi
发明人： Vijai Kumar Chhagan , Yelehanka Ramachandramurthy Pradeep , Mei Sheng Zhou , Henry Gerung , Simon Chooi
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28044 , H01L21/28114 , H01L29/41 , H01L29/42376 , H01L29/4941
摘要： A method for forming an extended metal gate without poly wrap around effects. A semiconductor structure is provided having a gate structure thereon. The gate structure comprising a gate dielectric layer, a gate silicon layer, a doped silicon oxide layer, and a disposable gate layer stacked sequentially. Spacers are formed on the sidewalls of the gate structure. A dielectric gapfill layer is formed over the semiconductor structure and the gate structure and planarized, stopping on the disposable gate layer. A first silicon nitride layer is formed over the disposable gate layer, and a dielectric layer is formed over the first silicon nitride layer. The dielectric layer is patterned to form a trench over the gate structure; therein the trench has a width greater than the width of the gate structure. The first silicon nitride layer in the bottom of the trench and the disposable gate layer are removed using one or more selective etching processes. The doped silicon oxide layer is removed using an etch with a high selectivity of doped silicon oxide to undoped silicon oxide. A barrier layer is formed over the gate silicon layer, and a metal gate layer is formed on the barrier layer; whereby the metal gate layer has a greater width than the gate structure.
摘要翻译：一种用于形成不具有聚环绕效应的延伸金属栅极的方法。提供其上具有栅极结构的半导体结构。栅极结构包括依次堆叠的栅极介电层，栅极硅层，掺杂氧化硅层和一次性栅极层。隔板形成在栅极结构的侧壁上。在半导体结构和栅极结构之上形成电介质间隙填充层，并在一次性栅极层上停止平坦化。在一次性栅极层上形成第一氮化硅层，并且在第一氮化硅层上形成电介质层。图案化电介质层以在栅极结构上形成沟槽; 其中沟槽的宽度大于栅极结构的宽度。使用一个或多个选择性蚀刻工艺去除沟槽底部中的第一氮化硅层和一次性栅极层。使用掺杂的氧化硅对未掺杂的氧化硅具有高选择性的蚀刻来去除掺杂的氧化硅层。在栅极硅层上形成阻挡层，在阻挡层上形成金属栅极层; 由此金属栅极层具有比栅极结构更大的宽度。

74. 发明授权

US06339021B1 Methods for effective nickel silicide formation 有权
标题翻译：有效的硅化镍形成方法
公开(公告)号：US06339021B1
公开(公告)日：2002-01-15
申请号：US09850992
申请日：2001-05-09
申请人： Wee Leng Tan , Kin Leong Pey , Simon Chooi
发明人： Wee Leng Tan , Kin Leong Pey , Simon Chooi
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： Methods for forming a high quality nickel silicide film in the fabrication of an integrated circuit are described. A semiconductor substrate is provided having silicon regions to be silicided wherein a native oxide layer forms on the silicon regions. A nickel layer is deposited overlying the silicon regions to be silicided. A titanium layer is deposited overlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium layer diffuse through the nickel layer and react with the native oxide layer and whereby the nickel is transformed to nickel silicide where it overlies the silicon regions and wherein the nickel not overlying the silicon regions is unreacted. In an alternative method, a titanium nitride layer over the titanium layer traps atmospheric oxygen freeing all of the titanium in the titanium layer to react with the underlying native oxide. The unreacted nickel layer is removed to complete formation of a nickel silicide film in the manufacture of an integrated circuit. In another method, a monolayer of titanium is deposited by atomic layer chemical vapor deposition underlying the nickel layer. The substrate is annealed whereby titanium atoms from the titanium monolayer react with the native oxide layer and whereby the the nickel is transformed to nickel silicide.
摘要翻译：描述了在制造集成电路中形成高质量硅化镍膜的方法。提供了具有要被硅化的硅区域的半导体衬底，其中在硅区域上形成自然氧化物层。沉积在要被硅化的硅区域上的镍层。沉积在镍层上的钛层。退火基板，由此来自钛层的钛原子通过镍层扩散并与天然氧化物层反应，由此将镍转化为硅化镍，其中它覆盖在硅区域上，并且其中未覆盖硅区域的镍是未反应的。在另一种方法中，钛层上方的氮化钛层捕获大气氧，释放钛层中的所有钛以与下面的天然氧化物反应。去除未反应的镍层以在集成电路的制造中完成硅化镍膜的形成。在另一种方法中，通过镍层下面的原子层化学气相沉积沉积单层的钛。退火基板，由此钛单层的钛原子与天然氧化物层反应，由此将镍转化为硅化镍。

75. 发明授权

US5893787A Application of fast etching glass for FED manufacturing 失效
标题翻译：快速蚀刻玻璃在FED制造中的应用
公开(公告)号：US5893787A
公开(公告)日：1999-04-13
申请号：US805877
申请日：1997-03-03
申请人： Lap Chan , Simon Chooi
发明人： Lap Chan , Simon Chooi
IPC分类号： H01J9/02
CPC分类号： H01J9/025
摘要： The microtip housing cavity in a cold cathode display was formed by selecting for the dielectric layer surrounding it a material whose etch rate (for the same etchant) was 3 to 20 times faster than the etch rate of the gate layer. Specifically, a gaseous etchant that included CHF.sub.3, CH.sub.4, CO, or CO and C.sub.4 F.sub.8 was used to form the cavity in a layer consisting of silicon oxide containing between about 3 and 10 weight % boron and between about 3 and 10 weight % phosphorus, deposited by chemical vapor deposition at pressures somewhat less than atmospheric (commonly referred to as SABPSG or sub-atmospheric boro-phosphosilicate glass). The gate layer consisted of phosphorus-doped polysilicon. Using this combination, once the gate opening had been etched, etching of the cavity proceeded very rapidly with little increase in the width of the gate opening. Thus the cavity was formed in a single mask, single etchant process.
摘要翻译：冷阴极显示器中的微尖端壳体腔通过选择围绕其的介电层形成，其蚀刻速率（相同蚀刻剂）的蚀刻速率比栅极层的蚀刻速率快3至20倍。具体地，使用包括CHF 3，CH 4，CO或CO和C 4 F 8的气体蚀刻剂在由含有约3至10重量％硼和约3至10重量％磷之间的氧化硅组成的层中形成空腔，通过化学气相沉积在小于大气压（通常称为SABPSG或次大气硼硅磷酸盐玻璃）的压力下沉积。栅极层由磷掺杂多晶硅组成。使用这种组合，一旦栅极开口被蚀刻，腔的蚀刻就非常迅速地进行，门开口的宽度几乎没有增加。因此，腔形成在单个掩模中，单一蚀刻过程。

76. 发明授权

US07179879B2 Poly(arylene ether) dielectrics 有权
标题翻译：聚（亚芳基醚）电介质
公开(公告)号：US07179879B2
公开(公告)日：2007-02-20
申请号：US11028774
申请日：2005-01-04
申请人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
发明人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
IPC分类号： C08G65/00
CPC分类号： C08G65/40 , C08G65/4006 , Y10T428/17 , Y10T428/31678
摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:
摘要翻译：本发明涉及在电子应用中用作低k电介质层的聚（亚芳基醚）和含有这种聚（亚芳基醚）的制品，其包含以下结构：其中n = 5至10000和一价Ar 1和二价Ar 2 H 2选自一组包含O，N，Se，S或Te的杂芳族化合物或上述组分的组合，包括但不限于：

77. 发明授权

US07166250B2 Poly(arylene ether) dielectrics 有权
公开(公告)号：US07166250B2
公开(公告)日：2007-01-23
申请号：US11028741
申请日：2005-01-04
申请人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
发明人： Christopher Lim , Siu Choon Ng , Hardy Chan , Simon Chooi , Mei Sheng Zhou
IPC分类号： B29C71/00 , C08G65/00
CPC分类号： C08G65/40 , C08G65/4006 , Y10T428/17 , Y10T428/31678
摘要： The present invention relates to poly(arylene ethers) used as low k dielectric layers in electronic applications and articles containing such poly(arylene ethers) comprising the structure: wherein n=5 to 10000 and monovalent Ar1 and divalent Ar2 are selected from a group of heteroaromatic compounds that incorporate O, N, Se, S, or Te or combinations of the aforesaid elements, including but not limited to:

78. 发明申请

US20060030095A1 Methods for elimination of arsenic based defects 有权
标题翻译：消除基于砷的缺陷的方法
公开(公告)号：US20060030095A1
公开(公告)日：2006-02-09
申请号：US10913214
申请日：2004-08-06
申请人： Yin-Min Goh , Simon Chooi , Teck Lim , Vincent Sih , Chian Sin , Ping Ee , Zainab Ismail , Cher Chua
发明人： Yin-Min Goh , Simon Chooi , Teck Lim , Vincent Sih , Chian Sin , Ping Ee , Zainab Ismail , Cher Chua
IPC分类号： H01L21/8238 , H01L21/4763
CPC分类号： H01L21/02057 , H01L21/02068 , H01L21/28518 , H01L21/76237 , H01L21/823814 , H01L21/823878 , H01L29/665 , H01L29/7833
摘要： Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation. Methods include wet etch procedures featuring hydrofluoric acid and hydrogen peroxide, as well as spin dry and dry etch procedures both employed post hydrofluoric acid treatment to remove re-deposited arsenic based defects.
摘要翻译：已经开发了制备用于硅化程序的源极/漏极区域的导电区域的方法。该方法在沉积随后形成的金属硅化物区域的金属组分之前，特征在于去除自然氧化物以及从导电表面去除沉积的基于砷的缺陷。注入用于N型源极/漏极区域的砷离子也被注入绝缘体区域，例如绝缘体填充的浅沟槽隔离区域。用作预硅化物制备方法的组分的氢氟酸循环可以以基于砷的缺陷的形式从浅沟槽隔离区释放砷，其又可以沉积在源极/漏极区的表面上。因此，本发明中描述的预硅化制备处理在金属硅化物形成之前特征是从导电表面除去天然氧化物和砷的缺陷。方法包括以氢氟酸和过氧化氢为特征的湿法蚀刻程序，以及在氢氟酸处理之后采用的旋转干燥和干蚀刻方法，以去除重新沉积的基于砷的缺陷。

79. 发明申请

US20050032392A1 Method to improve adhesion of dielectric films in damascene interconnects 失效
标题翻译：改善镶嵌互连中介质膜附着力的方法
公开(公告)号：US20050032392A1
公开(公告)日：2005-02-10
申请号：US10943101
申请日：2004-09-16
申请人： Luona Goh , Simon Chooi , Siew Toh , Tong Tay
发明人： Luona Goh , Simon Chooi , Siew Toh , Tong Tay
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/316 , H01L21/768 , C23C16/40 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/02164 , H01L21/02299 , H01L21/31058 , H01L21/3121 , H01L21/31612 , H01L21/76801 , H01L21/76807 , H01L21/76825
摘要： Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.
摘要翻译：实现了在大马士革工艺中改善低介电常数薄膜与其它介电薄膜和阻挡金属粘附性的方法。在一种方法中，低介电常数材料层沉积在衬底上。将硅离子注入到低介电常数材料层中。此后，将TEOS基氧化硅层沉积在低介电常数材料上，由此在低介电常数材料层和TEOS基氧化硅层之间具有良好的粘合性。在另一种方法中，将低介电常数材料层沉积在衬底上。沉积在低介电常数材料上的硅基电介质层，其中硅基电介质层不是氧化硅，从而在低介电常数材料层和硅基电介质层之间具有良好的粘合性。

80. 发明授权

US06797605B2 Method to improve adhesion of dielectric films in damascene interconnects 有权
标题翻译：改善镶嵌互连中介质膜附着力的方法
公开(公告)号：US06797605B2
公开(公告)日：2004-09-28
申请号：US09912737
申请日：2001-07-26
申请人： Luona Goh , Simon Chooi , Siew Lok Toh , Tong Earn Tay
发明人： Luona Goh , Simon Chooi , Siew Lok Toh , Tong Earn Tay
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/02164 , H01L21/02299 , H01L21/31058 , H01L21/3121 , H01L21/31612 , H01L21/76801 , H01L21/76807 , H01L21/76825
摘要： Method of improving adhesion of low dielectric constant films to other dielectric films and barrier metals in a damascene process are achieved. In one method, a low dielectric constant material layer is deposited on a substrate. Silicon ions are implanted into the low dielectric constant material layer. Thereafter, a TEOS-based silicon oxide layer is deposited overlying the low dielectric constant material whereby there is good adhesion between low dielectric constant material layer and the TEOS-based silicon oxide layer. In another method, a low dielectric constant material layer is deposited on a substrate. A silicon-based dielectric layer is deposited overlying the low dielectric constant material wherein the silicon-based dielectric layer is not silicon oxide whereby there is good adhesion between the low dielectric constant material layer and the silicon-based dielectric layer.
摘要翻译：实现了在大马士革工艺中改善低介电常数薄膜与其它介电薄膜和阻挡金属粘附性的方法。在一种方法中，低介电常数材料层沉积在衬底上。将硅离子注入到低介电常数材料层中。此后，将TEOS基氧化硅层沉积在低介电常数材料上，由此在低介电常数材料层和TEOS基氧化硅层之间具有良好的粘合性。在另一种方法中，将低介电常数材料层沉积在衬底上。沉积在低介电常数材料上的硅基电介质层，其中硅基电介质层不是氧化硅，从而在低介电常数材料层和硅基电介质层之间具有良好的粘合性。

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