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71. 发明申请

US20070108494A1 SEMICONDUCTOR DEVICE INCLUDING INSULATED GATE TYPE TRANSISTOR AND INSULATED GATE TYPE CAPACITANCE, AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：包括绝缘栅型晶体管和绝缘栅型电容器的半导体器件及其制造方法
公开(公告)号：US20070108494A1
公开(公告)日：2007-05-17
申请号：US11621177
申请日：2007-01-09
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

72. 发明授权

US07176515B2 Semiconductor device including insulated gate type transistor and insulated gate type capacitance having protruded portions 有权
标题翻译：包括绝缘栅型晶体管和具有突出部分的绝缘栅型电容器的半导体器件
公开(公告)号：US07176515B2
公开(公告)日：2007-02-13
申请号：US11220583
申请日：2005-09-08
申请人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
发明人： Shigenobu Maeda , Hiroyuki Takashino , Toshihide Oka
IPC分类号： H01L29/94
CPC分类号： H01L21/26586 , H01L21/74 , H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/1083 , H01L29/6659 , H01L29/7833 , H01L29/94
摘要： It is an object to obtain a semiconductor device having such a structure that respective electrical characteristics of an insulated gate type transistor and an insulated gate type capacitance are not deteriorated and a method of manufacturing the semiconductor device. An NMOS transistor Q1 and a PMOS transistor Q2 which are formed in an NMOS formation region A1 and a PMOS formation region A2 respectively have P− pocket regions 17 and N− pocket regions 27 in vicinal regions of extension portions 14e and 24e of N+ source-drain regions 14 and P+ source-drain regions 24, respectively. On the other hand, an N-type variable capacitance C1 and a P-type variable capacitance C2 which are formed in an N-type variable capacitance formation region A3 and a P-type variable capacitance formation region A4 respectively do not have a region of a reverse conductivity type which is adjacent to extraction electrode regions corresponding to the P− pocket regions 17 and the N− pocket regions 27.
摘要翻译：本发明的目的是获得具有绝缘栅型晶体管和绝缘栅型电容的各自电特性不劣化的结构的半导体器件以及半导体器件的制造方法。形成在NMOS形成区域A 1和PMOS形成区域A 2中的NMOS晶体管Q 1和PMOS晶体管Q 2分别具有P 0〜分别为N +源极 - 漏极区域14和P +源极 - 漏极区域24的延伸部分14e和24e的连续区域中的多个区域27。另一方面，形成在N型可变电容形成区域A 3和P型可变电容形成区域A 4中的N型可变电容C 1和P型可变电容C 2分别不具有与对应于凹穴区域17和凹陷区域27的引出电极区域相邻的反向导电型区域。

73. 发明授权

US07144764B2 Method of manufacturing semiconductor device having trench isolation 失效
标题翻译：制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US07144764B2
公开(公告)日：2006-12-05
申请号：US10949451
申请日：2004-09-27
申请人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
发明人： Takuji Matsumoto , Mikio Tsujiuchi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Shigeto Maegawa
IPC分类号： H01L21/762
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L29/78609 , H01L29/78612
摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
摘要翻译：本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3）。为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。

74. 发明申请

US20060267096A1 Method of designing semiconductor device, semiconductor device and recording medium 审中-公开
标题翻译：设计半导体器件，半导体器件和记录介质的方法
公开(公告)号：US20060267096A1
公开(公告)日：2006-11-30
申请号：US11483707
申请日：2006-07-11
申请人： Shigenobu Maeda , Yasuo Yamaguchi
发明人： Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/12
CPC分类号： H01L29/66772 , G06F17/5068 , H01L21/765 , H01L27/0207 , H01L27/1203 , H01L29/42372 , H01L29/42384 , H01L29/78615 , H01L29/78654
摘要： A semiconductor device including a transistor having an SOI structure the operating speed of which is not affected is provided. A MOS transistor having the SOI structure is formed which satisfies R·C·f
摘要翻译：提供一种半导体器件，其包括具有SOI结构的晶体管，其运行速度不受影响。形成具有SOI结构的MOS晶体管，其满足R.C.f <1，其中C是栅极电容（F），R是体电阻（Ω），f是时钟工作频率（Hz），f> = 500MHz。

75. 发明申请

US20060255389A1 Semiconductor device with decoupling capacitor and method of fabricating the same 审中-公开
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US20060255389A1
公开(公告)日：2006-11-16
申请号：US11392556
申请日：2006-03-30
申请人： Shigenobu Maeda
发明人： Shigenobu Maeda
IPC分类号： H01L29/94
CPC分类号： H01L21/765 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L27/1207
摘要： The semiconductor device includes a semiconductor layer formed on a semiconductor substrate (e.g., SOI or HOT), and an opening exposing the semiconductor substrate through semiconductor layer. A decoupling capacitor is formed in the opening and includes an epitaxial layer formed in the opening on the semiconductor substrate, and a gate structure disposed on the epitaxial layer.
摘要翻译：半导体器件包括形成在半导体衬底（例如，SOI或HOT）上的半导体层以及通过半导体层暴露半导体衬底的开口。在开口中形成去耦电容器，并且包括形成在半导体衬底上的开口中的外延层和设置在外延层上的栅极结构。

76. 发明申请

US20050218455A1 Low noise and high performance LSI device, layout and manufacturing method 有权
标题翻译：低噪声，高性能的LSI器件，布局和制造方法
公开(公告)号：US20050218455A1
公开(公告)日：2005-10-06
申请号：US11067836
申请日：2005-02-28
申请人： Shigenobu Maeda , Jeong Hwan Yang
发明人： Shigenobu Maeda , Jeong Hwan Yang
IPC分类号： H01L21/00 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L27/0922 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.
摘要翻译：在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能设备根据其运行模式进行优化。例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有没有施加应力。

77. 发明授权

US06538269B2 Gate array and manufacturing method of semiconductor integrated circuit using gate array 失效
标题翻译：门阵列和使用门阵列的半导体集成电路的制造方法
公开(公告)号：US06538269B2
公开(公告)日：2003-03-25
申请号：US09906094
申请日：2001-07-17
申请人： Shigenobu Maeda
发明人： Shigenobu Maeda
IPC分类号： H01L2710
CPC分类号： H01L27/11807
摘要： In a gate array, a gate length is measured by dividing gate electrodes into groups according to their materials to distinguish between those groups. The shape of a contact pad portion (5) of a gate electrode (4) differs according to the groups. A difference described here appears as shape such as cutouts (6a-6c) or projections (6d-6f), which is distinguishable by a scanning electron microscope, for example.
摘要翻译：在栅极阵列中，通过根据栅极电极的材料将栅电极分成组来测量栅极长度，以区分这些组。栅电极（4）的接触焊盘部（5）的形状根据组而不同。这里描述的差异表现为例如通过扫描电子显微镜可区分的切口（6a-6c）或突起（6d-6f）的形状。

78. 发明授权

US06509211B2 Semiconductor device having SOI structure and method of fabricating the same 失效
标题翻译：具有SOI结构的半导体器件及其制造方法
公开(公告)号：US06509211B2
公开(公告)日：2003-01-21
申请号：US09790699
申请日：2001-02-23
申请人： Yasuo Yamaguchi , Shigenobu Maeda , Iijong Kim
发明人： Yasuo Yamaguchi , Shigenobu Maeda , Iijong Kim
IPC分类号： H01L21339
CPC分类号： H01L29/78696 , H01L21/26506 , H01L21/26586 , H01L27/12 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78621
摘要： A semiconductor device having an SOI structure capable of effectively preventing diffusion of an impurity from a source/drain region on an endmost portion of a silicon layer under a gate electrode is disclosed. In this semiconductor device, nitrogen is introduced into at least either a source/drain region or an end portion of a semiconductor layer located under a gate electrode, and the concentration profile of the nitrogen has a first concentration peak at least in either one of an endmost portion of the source/drain region in the direction where the gate electrode extends and an endmost portion of the semiconductor layer located under the gate electrode. Due to this concentration profile of nitrogen, point defects or the like serving as mediation for diffusion of an impurity are trapped, whereby diffusion of the impurity from the source/drain region is inhibited as a result. Thus, generation of an abnormal leakage current or the like is prevented.
摘要翻译：公开了一种具有SOI结构的半导体器件，该SOI结构能够有效地防止杂质从源极/漏极区域扩散到栅电极下方的硅层的最末端部分。在该半导体器件中，将氮气引入位于栅电极下方的半导体层的源极/漏极区域或端部的至少一个中，并且氮的浓度分布至少具有第一浓度峰值源极/漏极区域在栅电极延伸的方向的最末端部分和位于栅电极下方的半导体层的最末端部分。由于氮的浓度分布，作为用于杂质扩散的介质的点缺陷等被捕获，结果导致杂质从源/漏区的扩散受到抑制。因此，防止产生异常的漏电流等。

79. 发明授权

US06486513B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06486513B1
公开(公告)日：2002-11-26
申请号：US09464436
申请日：1999-12-16
申请人： Takuji Matsumoto , Shigenobu Maeda
发明人： Takuji Matsumoto , Shigenobu Maeda
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/78612 , H01L29/78621
摘要： An SOI layer is provided in a buried oxide film and a source and a drain are provided on the upper surface of the SOI layer so that they are kept from contact with the buried oxide film. A depletion layer formed by the source, the drain, and the SOI layer extends to reach the buried oxide film, so parasitic capacitance is reduced. This structure achieves an SOIMOS transistor capable of reducing junction capacitance at low drain voltage.
摘要翻译：在掩埋氧化膜中设置SOI层，在SOI层的上表面设置源极和漏极，使其不与埋入氧化物膜接触。由源极，漏极和SOI层形成的耗尽层延伸以到达掩埋氧化物膜，因此寄生电容降低。该结构实现了能够在低漏极电压下降低结电容的SOIMOS晶体管。

80. 发明授权

US06358815B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06358815B2
公开(公告)日：2002-03-19
申请号：US09886031
申请日：2001-06-22
申请人： Shigenobu Maeda
发明人： Shigenobu Maeda
IPC分类号： H01L2176
CPC分类号： H01L29/66772 , H01L21/306 , H01L21/7624 , H01L21/76264 , H01L21/76283 , H01L29/1079 , H01L29/78603 , Y10S438/96
摘要： A semiconductor device comprises a silicon region (1) of the first conductivity type, a porous silicon layer (2) formed inside the silicon region (1) as a buried layer and a source region (3a) and a drain region (4a) of the second conductivity type different from the first conductivity type selectively formed in an upper surface of the silicon region (1). Bottom surfaces of the source region (3a) and the drain region (4a) are located adjacently above an upper surface of the porous silicon layer (2). As a result, depletion layers (8) in pn junctions between the silicon region (1) and the bottom surfaces of the source region (3a) and the drain region (4a) reach the inside of the porous silicon layer (2). With this structure, a semiconductor device which achieves a faster operation and lower power consumption while ensuring stability in operation of a MOSFET and a method of manufacturing the same are provided.
摘要翻译：半导体器件包括第一导电类型的硅区域（1），形成在作为掩埋层的硅区域（1）内的多孔硅层（2）和源极区域（3a）和漏极区域（4a）不同于在硅区域（1）的上表面中选择性地形成的第一导电类型的第二导电类型。源极区域（3a）和漏极区域（4a）的底表面邻近位于多孔硅层（2）的上表面上方。结果，硅区域（1）和源极区域（3a）和漏极区域（4a）的底表面之间的pn结中的耗尽层（8）到达多孔硅层（2）的内部。利用这种结构，提供了一种在确保MOSFET的操作中的稳定性的同时实现更快的操作和更低功耗的半导体器件及其制造方法。

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