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1. 发明申请

US20140042974A1 DETACHABLE BATTERY MODULE, AND METHOD AND APPARATUS FOR THE CHARGE EQUALIZATION OF A BATTERY STRING USING SAME 审中-公开
标题翻译：可拆卸电池模块，以及使用相同电池充电均衡化的方法和装置
公开(公告)号：US20140042974A1
公开(公告)日：2014-02-13
申请号：US14113257
申请日：2011-04-22
申请人： Jeong Hwan Yang , Gun-Woo Moon , Chol-Ho Kim , Moon-Young Kim
发明人： Jeong Hwan Yang , Gun-Woo Moon , Chol-Ho Kim , Moon-Young Kim
IPC分类号： H02J7/00
CPC分类号： H02J7/0014 , G01R19/16542 , G01R31/3835 , G01R31/396 , H01M10/441 , H01M10/482 , H02J7/0018 , H02J2007/005
摘要： Provided are a detachable battery module and a charge equalization method and apparatus for a battery string. According to the exemplary embodiments of the present invention, the charge equalization apparatus are modularized by being divided into the master unit and the slave unit, such that the charge equalization apparatus may be expanded and contracted independent of the number of batteries, the circuits are separated for each module, such that the circuits may be easily implemented, and when the circuits are damaged, only the damaged module is replaced, such that the effective countermeasure may be performed.
摘要翻译：提供一种用于电池串的可拆卸电池模块和电荷均衡方法和装置。根据本发明的示例性实施例，电荷均衡装置通过分为主单元和从单元进行模块化，使得电荷均衡装置可以独立于电池数量而扩展和收缩，电路分离对于每个模块，使得电路可以容易地实现，并且当电路被损坏时，只有损坏的模块被替换，使得可以执行有效的对策。

2. 发明申请

US20130176041A1 INSULATION RESISTANCE MEASUREMENT CIRCUIT HAVING SELF-TEST FUNCTION WITHOUT GENERATING LEAKAGE CURRENT 有权
标题翻译：具有不产生泄漏电流的自检功能的绝缘电阻测量电路
公开(公告)号：US20130176041A1
公开(公告)日：2013-07-11
申请号：US13823268
申请日：2011-09-16
申请人： Jeong Hwan Yang
发明人： Jeong Hwan Yang
IPC分类号： G01R27/14
CPC分类号： G01R27/14 , B60L3/0069 , G01R27/025 , G01R31/025 , G01R35/00
摘要： Provided is an insulation resistance measurement circuit including: a source resistance unit including a first source resistance unit connected to a positive terminal of an insulation resistance measurement battery and a second source resistance unit connected to a negative terminal of the insulation resistance measurement battery and the first source resistance unit; a voltage sensing unit including a first operational amplifier sensing the voltage of the first source resistance unit, as a first voltage, and the voltage of the second source resistance unit, as a second voltage; a leakage current interrupting unit including a first switch connected to the positive terminal of the insulation resistance measurement battery and the first source resistance unit and a second switch connected to the negative terminal of the insulation resistance measurement battery and the second source resistance unit; a measurement circuit testing unit including a third switch connected to the first operational amplifier and a first voltage source and a fourth switch connected to the second operational amplifier and a second voltage source; and an insulation resistance measurement unit measuring insulation resistance of the insulation resistance measurement battery through the first and second voltages.
摘要翻译：提供一种绝缘电阻测量电路，包括：源极电阻单元，包括连接到绝缘电阻测量电池的正极端子的第一源极电阻单元和连接到绝缘电阻测量电池的负极端子的第二源极电阻单元，源电阻单元; 电压检测单元，其包括将第一源极电阻单元的电压作为第一电压和第二源极电阻单元的电压作为第二电压感测的第一运算放大器; 泄漏电流中断单元，包括连接到绝缘电阻测量电池的正极端子的第一开关和第一源极电阻单元以及连接到绝缘电阻测量电池和第二源极电阻单元的负极端子的第二开关; 测量电路测试单元，包括连接到第一运算放大器的第三开关和连接到第二运算放大器的第一电压源和第四开关和第二电压源; 绝缘电阻测量单元，通过第一和第二电压来测量绝缘电阻测量电池的绝缘电阻。

3. 发明授权

US07964454B2 Low noise and high performance LSI device, layout and manufacturing method 有权
标题翻译：低噪声，高性能的LSI器件，布局和制造方法
公开(公告)号：US07964454B2
公开(公告)日：2011-06-21
申请号：US11981153
申请日：2007-10-31
申请人： Shigenobu Maeda , Jeong Hwan Yang
发明人： Shigenobu Maeda , Jeong Hwan Yang
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L27/0207 , H01L27/092 , H01L27/1052 , H01L29/0649 , H01L29/665 , H01L29/7833 , H01L29/7842 , H01L29/7843 , H01L29/7845 , H01L29/7848
摘要： In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.
摘要翻译：在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能设备根据其运行模式进行优化。例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有没有施加应力。

4. 发明申请

US20080211022A1 Semiconductor device having a triple gate transistor and method for manufacturing the same 有权
标题翻译：具有三栅极晶体管的半导体器件及其制造方法
公开(公告)号：US20080211022A1
公开(公告)日：2008-09-04
申请号：US12008232
申请日：2008-01-09
申请人： Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
发明人： Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/7854 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7855
摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.
摘要翻译：在能够减少NBTI的半导体及其制造方法中，多栅极晶体管包括有源区，栅极电介质，有源区中的沟道和栅电极，并形成在半导体晶片上。有源区具有顶表面和侧表面，并且在第一方向上定向。栅电介质形成在有源区的顶表面和侧表面上。通道形成在有源区域的顶表面和侧表面中。栅极电极形成在对应于沟道的栅极电介质上并垂直于有源区域排列，使得电流在第一方向上流动。在本发明的一个方面中，在具有第一方向的第一取向指示器的支撑基板上形成具有第二方向的第二取向指示器的SOI层。在SOI层上形成多栅极晶体管。第一方向和第二方向相同，或者第一方向相对于第二方向成45度。在本发明的另一方面，活性区域的顶表面和侧表面的交叉是弯曲的，进一步减少了NBTI。在本发明的另一方面，多栅晶体管形成在体晶片的浅沟槽隔离区上。

5. 发明申请

US20060232191A1 Gate-controlled electron-emitter array panel, active matrix display including the same, and method of manufacturing the panel 审中-公开
标题翻译：门控电子发射器阵列面板，包括相同的有源矩阵显示器以及制造面板的方法
公开(公告)号：US20060232191A1
公开(公告)日：2006-10-19
申请号：US11377463
申请日：2006-03-16
申请人： Jeong-Hwan Yang
发明人： Jeong-Hwan Yang
IPC分类号： H01J1/62
CPC分类号： H01J29/02 , H01J29/467 , H01J29/48 , H01J31/127
摘要： An active matrix display comprising an array of gate-controlled surface-conduction electron-emitter devices (GC_SEDs). Each gate-controlled_surface-conduction electron-emitter device (GC_SED) comprises a first electrode, and a pair of (second and third) electrodes that are insulated from the first electrode and that are spaced apart from each other to bound an electron-emitting area overlapping the first electrode. The potential barrier in the electron-emitting area (slit) between the second and third electrodes is modulated (controlled, switched) by applying a voltage to the first electrode that serves as a gate that effectively controls the tunneling of the electrons, between the second and third electrodes. Efficient electron tunneling is allowed through modulation of potential barrier by the first electrode functioning as a gate even though the distance (width of the electron-emitting area, slit) between the second and third electrodes may be significantly more than 10 nanometers.
摘要翻译：一种有源矩阵显示器，包括栅极控制的表面传导电子发射器件（GC_SED）阵列。每个栅极控制的表面传导电子发射器件（GC_SED）包括第一电极和一对（第二和第三）电极，其与第一电极绝缘并且彼此间隔开以结合电子发射区域与第一电极重叠。在第二和第三电极之间的电子发射区（狭缝）中的势垒通过向用作有效控制电子的隧穿的第一电极施加电压而被调制（控制，切换），第二和第三电极。即使第二电极和第三电极之间的距离（电子发射区域，狭缝的宽度）可能明显大于10纳米，通过用作栅极的第一电极的势垒的调制允许有效的电子隧穿。

6. 发明申请

US20050116218A1 Non-planar transistor having germanium channel region and method of manufacturing the same 有权
标题翻译：具有锗沟道区域的非平面晶体管及其制造方法
公开(公告)号：US20050116218A1
公开(公告)日：2005-06-02
申请号：US10997440
申请日：2004-11-23
申请人： Jeong-hwan Yang
发明人： Jeong-hwan Yang
IPC分类号： H01L29/41 , H01L21/336 , H01L29/78 , H01L29/786 , H01L29/06
CPC分类号： H01L29/785 , H01L29/1054 , H01L29/66795 , H01L29/78687
摘要： Provided is a non-planar transistor with a multi-gate structure that includes a germanium channel region, and a method of manufacturing the same. The non-planar transistor includes a silicon body and a channel region that covers exposed surfaces of the silicon body. The channel region is formed of a germanium layer and includes a first channel region and a second channel region. In order to form the germanium channel region, a mesa type active region is formed on the substrate, and a germanium layer is formed to cover two sidewalls and an upper surface of the active region.
摘要翻译：提供一种具有多栅极结构的非平面晶体管，其包括锗沟道区域及其制造方法。非平面晶体管包括硅体和覆盖硅体的暴露表面的沟道区域。沟道区由锗层形成，并包括第一沟道区和第二沟道区。为了形成锗通道区域，在基板上形成台面型有源区，形成锗层以覆盖有源区的两个侧壁和上表面。

7. 发明授权

US06806157B2 Metal oxide semiconductor field effect transistor for reducing resistance between source and drain and method for fabricating the same 有权
标题翻译：用于降低源极和漏极之间的电阻的金属氧化物半导体场效应晶体管及其制造方法
公开(公告)号：US06806157B2
公开(公告)日：2004-10-19
申请号：US10375437
申请日：2003-02-27
申请人： Jeong-hwan Yang , Young-wug Kim
发明人： Jeong-hwan Yang , Young-wug Kim
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y10S257/90
摘要： A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.
摘要翻译：用于降低源极和漏极之间的电阻的MOS场效应晶体管包括依次形成在半导体衬底上的栅绝缘层和栅电极，包括形成在栅极两侧的半导体衬底的上部的深源极/漏极区电极。源极/漏极延伸区域形成在半导体衬底的从深源极/漏极区域延伸到栅极电极下方的沟道区域的上部，以比深的源极/漏极区域更薄。在每个深源极/漏极区域的表面上形成具有第一厚度的第一硅化物层。形成具有比第一硅化物层的第一厚度薄的第二厚度的第二硅化物层，以在每个源极/漏极延伸区域的预定上部从第一硅化物层延伸。

8. 发明授权

US09069024B2 Insulation resistance measurement circuit having self-test function without generating leakage current 有权
标题翻译：具有自检功能的绝缘电阻测量电路，不产生漏电流
公开(公告)号：US09069024B2
公开(公告)日：2015-06-30
申请号：US13823268
申请日：2011-09-16
申请人： Jeong Hwan Yang
发明人： Jeong Hwan Yang
IPC分类号： G01R27/14 , G01R27/02 , B60L3/00 , G01R31/02
CPC分类号： G01R27/14 , B60L3/0069 , G01R27/025 , G01R31/025 , G01R35/00
摘要： An insulation resistance measurement circuit in which switching of first and second switches is controlled such that a leakage current may not be generated in measuring insulation resistance, and voltages output through first and second operational amplifiers are measured after opening the first and second switches and closing third and fourth switches for self-testing of the insulation resistance measurement circuit.
摘要翻译：一种绝缘电阻测量电路，其中控制第一和第二开关的开关，使得在测量绝缘电阻时可能不产生泄漏电流，并且在打开第一和第二开关并闭合第三个之后测量通过第一和第二运算放大器输出的电压以及用于绝缘电阻测量电路的自检的第四开关。

9. 发明授权

US08618629B2 Apparatus and method for through silicon via impedance matching 有权
标题翻译：用于硅通过阻抗匹配的装置和方法
公开(公告)号：US08618629B2
公开(公告)日：2013-12-31
申请号：US12576094
申请日：2009-10-08
申请人： Jonghae Kim , Jeong Hwan Yang , Matthew M. Nowak
发明人： Jonghae Kim , Jeong Hwan Yang , Matthew M. Nowak
IPC分类号： H01L27/08 , H01L21/00
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/3011
摘要： Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit.
摘要翻译：提出了用于匹配倒装芯片电路组件中的阻抗的方法和装置。用于匹配倒装芯片电路组件中的阻抗的装置可以包括与第一管芯相连的第一电路和将第一电路耦合到第二电路的通硅通孔（TSV）。该装置还可以包括插在TSV和第二电路之间的第一阻抗匹配电感器。用于匹配倒装芯片电路组件中的阻抗的方法可以包括提供具有第一电路的管芯，并在管芯上形成TSV。该方法还可以包括提供第二电路并形成插在TSV和第二电路之间的第一阻抗匹配电感器。

10. 发明申请

US20120168828A1 SEMICONDUCTOR DEVICE HAVING A TRIPLE GATE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
公开(公告)号：US20120168828A1
公开(公告)日：2012-07-05
申请号：US13417744
申请日：2012-03-12
申请人： Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
发明人： Shigenobu Maeda , Jeong Hwan Yang , Junga Choi
IPC分类号： H01L29/78
CPC分类号： H01L29/7854 , H01L29/045 , H01L29/66795 , H01L29/785 , H01L29/7855
摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction.

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