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71. 发明授权

US06601196B1 Method and apparatus for debugging ternary and high speed busses 有权
标题翻译：用于调试三元和高速总线的方法和装置
公开(公告)号：US06601196B1
公开(公告)日：2003-07-29
申请号：US09608449
申请日：2000-06-29
申请人： Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
发明人： Sanjay Dabral , Ramesh Senthinathan , Ming Zeng , Keith Self , Ernest Khaw , Chung-Wai Yue
IPC分类号： G06F1100
CPC分类号： G06F11/221
摘要： An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.
摘要翻译：一种用于调试总线的装置和方法，包括插入监视总线上的两个设备之间传输的数据的设备，使得总线被分成两个总线，当数据被复制以传输到诊断设备时，数据在两辆巴士。

72. 发明授权

US06515534B2 Enhanced conductivity body biased PMOS driver 有权
公开(公告)号：US06515534B2
公开(公告)日：2003-02-04
申请号：US09475648
申请日：1999-12-30
申请人： Sanjay Dabral
发明人： Sanjay Dabral
IPC分类号： H03K301
CPC分类号： H03K19/0027 , H01L29/78 , H03K2217/0018
摘要： According to one embodiment of the present invention a method for biasing a body of a transistor. The method includes detecting a voltage applied to a terminal of a transistor and coupling a biasing voltage to the body based upon the detected voltage.

73. 发明授权

US6137143A Diode and transistor design for high speed I/O 失效
标题翻译：用于高速I / O的二极管和晶体管设计
公开(公告)号：US6137143A
公开(公告)日：2000-10-24
申请号：US107351
申请日：1998-06-30
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002
摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.
摘要翻译：一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护电路到性能电路。

74. 发明授权

US5781258A Assembling and sealing large, hermetic and semi-hermetic, h-tiled, flat-paneled displays 失效
标题翻译：组装和密封大，密封和半密封，h平铺的平板显示器
公开(公告)号：US5781258A
公开(公告)日：1998-07-14
申请号：US662618
申请日：1996-06-13
申请人： Sanjay Dabral , Raymond G. Greene , John P. Koons , Donald P. Seraphim , Boris Yost
发明人： Sanjay Dabral , Raymond G. Greene , John P. Koons , Donald P. Seraphim , Boris Yost
IPC分类号： G02F1/1333 , G02F1/1339 , G02F1/133
CPC分类号： G02F1/1339 , G02F1/13336
摘要： The present invention features flat-panel displays having a mosaic of tiles, and methods of constructing and sealing them. Sealing designs are described to maintain appropriate vacuum levels for FEDs, PFPDs and LCDs. The mosaic of tiles forming a flat-panel display may include subassembly tiles, with each consisting of two, unsealed, substantially parallel plates having a structure positioned between them; these are known as s-tiles. The tiles may be enclosed by a cover plate and backplate. Non-permeable material may be deposited on the cover plate and the backplate, with solderable metal overlaid on the non-permeable material. A metallized, non-permeable spacer/connector is also located between the cover plate and backplate for hermetically sealing the perimeter of the display. A set of electrical-interconnection, metal feed-throughs can also be positioned in the non-permeable spacer/connector. A flat-panel display may also be made up of half-tiles (h-tiles), with each including an individual bottom plate with a structure disposed on them. The mosaic of tiles also has a cover plate that is shared in common with all of the h-tiles. This common cover plate for each type of FPD integrates functions such as masking, screening, color filtering, polarizing and interconnecting. Also provided in the invention is a method for testing the seal of the flat-panel display. A simulated cover plate is attached via a polymeric seal, so that a structure enclosed between the two plates may be evacuated. When a gas is applied around the display seal, its leakage rate is measured, so as to locate the site of defects.
摘要翻译：本发明的特征在于具有瓦片马赛克的平板显示器，以及构造和密封它们的方法。描述了密封设计，以保持FED，PFPD和LCD的适当真空度。形成平板显示器的瓷砖的马赛克可以包括子组件瓦片，每个瓦片包括两个未密封的基本平行的板，其具有位于它们之间的结构; 这些被称为s-tiles。瓦片可以由盖板和背板封闭。不可渗透的材料可以沉积在盖板和背板上，可焊接的金属覆盖在不可渗透的材料上。金属化的，不可渗透的间隔件/连接器也位于盖板和背板之间，用于气密地密封显示器的周边。一组电互连，金属馈通也可以定位在不可渗透的间隔件/连接器中。平板显示器也可以由半瓦片（h瓦片）组成，每个瓦片包括设置在其上的结构的单个底板。瓷砖的马赛克还具有与所有h瓦片共享的盖板。这种用于每种类型的FPD的普通盖板集成了诸如掩模，筛选，滤色，偏振和互连的功能。本发明还提供了一种用于测试平板显示器的密封件的方法。模拟盖板通过聚合物密封件连接，使得封闭在两个板之间的结构可以被抽空。当在显示器密封件周围施加气体时，测量其泄漏率，以便定位缺陷位置。

75. 发明授权

US08315347B2 I/O link with configurable forwarded and derived clocks 有权
标题翻译： I / O链接与可配置的转发和派生时钟
公开(公告)号：US08315347B2
公开(公告)日：2012-11-20
申请号：US12592705
申请日：2009-12-01
申请人： Karthisha S. Canagasaby , Sanjay Dabral
发明人： Karthisha S. Canagasaby , Sanjay Dabral
IPC分类号： H04L7/02
CPC分类号： H04L7/0054 , H04L7/0025 , H04L7/0337
摘要： An electronic communications receiver includes a derived clock signal circuit operable to receive a data signal and to derive a derived clock signal from the received data signal. A separate forwarded clock signal circuit is further operable to receive a forwarded clock signal, and a clock management circuit is operable to receive signals from the derived clock signal circuit and the forwarded clock signal circuit, and to output an output clock signal.
摘要翻译：电子通信接收机包括导出的时钟信号电路，其可操作以接收数据信号并从接收的数据信号导出导出的时钟信号。单独转发的时钟信号电路还可操作以接收转发的时钟信号，并且时钟管理电路可操作以从导出的时钟信号电路和转发的时钟信号电路接收信号，并输出输出时钟信号。

76. 发明授权

US08250416B2 Redundant acknowledgment in loopback entry 有权
标题翻译：环回输入中的冗余确认
公开(公告)号：US08250416B2
公开(公告)日：2012-08-21
申请号：US12649729
申请日：2009-12-30
申请人： Tim Frodsham , Zale Schoenborn , Sanjay Dabral , Muraleedhara Navada
发明人： Tim Frodsham , Zale Schoenborn , Sanjay Dabral , Muraleedhara Navada
IPC分类号： G01R31/28
CPC分类号： G01R31/31716
摘要： Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.
摘要翻译：描述了在双向通信总线之间进行环回测试的代理之间的冗余确认。在一个示例中，在包括耦合到双向通信总线的通信代理的处理器中，通信代理向第二代理发起回送通信，向第二代理发送包括冗余确认序列的分组，接收包括冗余确认序列的分组从第二代理循环回来，确定接收的冗余确认序列是否有效，向第二代理发送测试序列，接收循环的测试序列，如果接收到的冗余确认序列被确定为有效，则检查接收到的测试顺序。

77. 发明授权

US08204067B2 Technique for lane virtualization 有权
标题翻译：车道虚拟化技术
公开(公告)号：US08204067B2
公开(公告)日：2012-06-19
申请号：US10891348
申请日：2004-07-13
申请人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
发明人： Naveen Cherukuri , Jeffrey R. Wilcox , Sanjay Dabral , David S. Dunning , Tim Frodsham , Theodore Z. Schoenborn
IPC分类号： H04L12/56
CPC分类号： G06F13/4018 , G06F13/4009 , Y02D10/14 , Y02D10/151
摘要： A technique to perform virtualization of lanes within a common system interface (CSI) link. More particularly, embodiments described herein relate to virtualizing interconnective paths between two or more electronic devices residing in an electronic network.
摘要翻译：在公共系统接口（CSI）链路中执行通道虚拟化的技术。更具体地，这里描述的实施例涉及虚拟化驻留在电子网络中的两个或多个电子设备之间的互连路径。

78. 发明授权

US08195996B2 Apparatuses, systems and methods for detecting errors in data streams on point-to-point serial links 有权
标题翻译：用于检测点对点串行链路上的数据流中的错误的装置，系统和方法
公开(公告)号：US08195996B2
公开(公告)日：2012-06-05
申请号：US12115360
申请日：2008-05-05
申请人： Timothy Frodsham , Zale T. Schoenborn , Sanjay Dabral , Murateendhara Navada
发明人： Timothy Frodsham , Zale T. Schoenborn , Sanjay Dabral , Murateendhara Navada
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： H04L1/242
摘要： Methods, apparatuses and systems for physical link error data capture and analysis. A receiver is coupled to receive a data stream via a point-to-point serial link. A control circuit is coupled with the receiver to cause the receiver to selectively sample the data stream according to an offset parameter and an interval parameter. Comparison circuitry compares the data stream sample to expected data values to determine a bit error rate.
摘要翻译：用于物理链路错误数据捕获和分析的方法，设备和系统。接收器被耦合以经由点对点串行链路接收数据流。控制电路与接收器耦合，使得接收机根据偏移参数和间隔参数选择性地采样数据流。比较电路将数据流样本与预期数据值进行比较，以确定误码率。

79. 发明授权

US07804890B2 Method and system for response determinism by synchronization 有权
标题翻译：通过同步的响应确定性的方法和系统
公开(公告)号：US07804890B2
公开(公告)日：2010-09-28
申请号：US11166030
申请日：2005-06-23
申请人： Muraleedhara H. Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris D. Matthews , Chris C. Gianos , Rahul R. Shah , Theodore Z. Schoenborn
发明人： Muraleedhara H. Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris D. Matthews , Chris C. Gianos , Rahul R. Shah , Theodore Z. Schoenborn
IPC分类号： H04B3/46
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/0041
摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.
摘要翻译：关于改进对测试矢量的集成设备确定性响应的讨论。例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。

80. 发明授权

US07711939B2 Serial link apparatus, method, and system 有权
标题翻译：串行链路设备，方法和系统
公开(公告)号：US07711939B2
公开(公告)日：2010-05-04
申请号：US11171114
申请日：2005-06-30
申请人： Karthisha S. Canagasaby , Ken Drottar , David S. Dunning , Sanjay Dabral
发明人： Karthisha S. Canagasaby , Ken Drottar , David S. Dunning , Sanjay Dabral
IPC分类号： H03K3/00
CPC分类号： H04L25/0282
摘要： A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.
摘要翻译：源端接串行链路可以通过在分相序列中打开多个电流模式驱动器从低功率模式恢复，其中相序序列与电源网络的谐振特性相关。

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