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1. 发明授权

US6137143A Diode and transistor design for high speed I/O 失效
标题翻译：用于高速I / O的二极管和晶体管设计
公开(公告)号：US6137143A
公开(公告)日：2000-10-24
申请号：US107351
申请日：1998-06-30
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002
摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.
摘要翻译：一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护电路到性能电路。

2. 发明授权

US07250333B2 Method of fabricating a linearized output driver and terminator 有权
标题翻译：制造线性化输出驱动器和终端器的方法
公开(公告)号：US07250333B2
公开(公告)日：2007-07-31
申请号：US10394977
申请日：2003-03-20
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L21/8234 , H01L21/8244
CPC分类号： H01L29/66659 , H01L29/7835 , Y02P80/30
摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.
摘要翻译：描述了用于线性化输出驱动器和终止器的方法和装置。在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

3. 发明授权

US07012304B1 Diode and transistor design for high speed I/O 失效
公开(公告)号：US07012304B1
公开(公告)日：2006-03-14
申请号：US09651385
申请日：2000-08-29
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

4. 发明授权

US6090650A Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances 失效
公开(公告)号：US6090650A
公开(公告)日：2000-07-18
申请号：US940303
申请日：1997-09-30
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： G06F13/40 , H01L21/8234 , H01L21/8238 , H01L29/423 , H03L7/00 , H01L21/337
CPC分类号： H03L7/00 , G06F13/4072 , H01L21/823418 , H01L21/823437 , H01L21/823828 , H01L29/4238 , H01L2924/0002
摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

5. 发明授权

US06480059B2 Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances 失效
标题翻译：减少由制造工艺公差引起的I / O电路和时钟驱动器中的时序偏差的方法
公开(公告)号：US06480059B2
公开(公告)日：2002-11-12
申请号：US09473855
申请日：1999-12-28
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L2500
CPC分类号： H03L7/00 , G06F13/4072 , H01L21/823418 , H01L21/823437 , H01L21/823828 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.
摘要翻译：降低场效应晶体管器件中的随机处理引起的时序变化的方法包括提供具有有源区的半导体衬底，以及形成在有源区的一部分上具有栅极的晶体管，栅极具有第一支脚和第二条腿在另一方面，提出了一种改进严格匹配电路的定时偏移的方法。在本发明的另一方面，提出了一种场效应晶体管和集成电路器件，其可用于在存在随机制造或工艺引起的变化的情况下改善时序鲁棒性。

6. 发明授权

US06646324B1 Method and apparatus for a linearized output driver and terminator 有权
标题翻译：线性化输出驱动器和终端器的方法和装置
公开(公告)号：US06646324B1
公开(公告)日：2003-11-11
申请号：US09609434
申请日：2000-06-30
申请人： Sanjay Dabral , Krishna Seshan
发明人： Sanjay Dabral , Krishna Seshan
IPC分类号： H01L2900
CPC分类号： H01L29/66659 , H01L29/7835 , Y02P80/30
摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.
摘要翻译：描述了用于线性化输出驱动器和终止器的方法和装置。在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

7. 发明授权

US08143911B2 Input/output driver swing control and supply noise rejection 有权
标题翻译：输入/输出驱动器摆幅控制和电源噪声抑制
公开(公告)号：US08143911B2
公开(公告)日：2012-03-27
申请号：US12060251
申请日：2008-03-31
申请人： Zuoguo Wu , Feng Chen , Sanjay Dabral
发明人： Zuoguo Wu , Feng Chen , Sanjay Dabral
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H04L25/0276
摘要： In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
摘要翻译：通常，在一个方面，本公开描述了一种具有平均器以接收发射机的差分输出电压并产生平均发射机输出电压的装置。比较器将平均发射机输出电压与参考电压进行比较，并产生它们之间的差值。积分器将整合平均发射机输出电压和参考电压随时间的差异。积分差值被反馈给发射机以偏置发射机。

8. 发明申请

US20120011276A1 Dynamically Modulating Link Width 有权
标题翻译：动态调节链路宽度
公开(公告)号：US20120011276A1
公开(公告)日：2012-01-12
申请号：US13240546
申请日：2011-09-22
申请人： Naveen Cherukuri , Aaron T. Spink , Phanindra Mannaya , Tim Frodsham , Jeffrey R. Wilcox , Sanjay Dabral , David Dunning , Theodore Z. Schoenborn
发明人： Naveen Cherukuri , Aaron T. Spink , Phanindra Mannaya , Tim Frodsham , Jeffrey R. Wilcox , Sanjay Dabral , David Dunning , Theodore Z. Schoenborn
IPC分类号： G06F15/173
CPC分类号： H04L67/141 , G06F13/4265 , H04L65/60 , Y02D10/14 , Y02D10/151
摘要： Systems and methods of managing a link provide for receiving a remote width capability during a link initialization, the remote width capability corresponding to a remote port. A link between a local port and the remote port is operated at a plurality of link widths in accordance with the remote width capability.
摘要翻译：管理链路的系统和方法提供了在链路初始化期间接收远程宽度能力，即对应于远程端口的远程宽度能力。根据远程宽度能力，本地端口和远程端口之间的链路以多个链路宽度进行操作。

9. 发明授权

US07907418B2 Circuit board including stubless signal paths and method of making same 有权
标题翻译：电路板包括无铅信号路径及其制作方法
公开(公告)号：US07907418B2
公开(公告)日：2011-03-15
申请号：US12628778
申请日：2009-12-01
申请人： Pascal Meier , Sanjay Dabral
发明人： Pascal Meier , Sanjay Dabral
IPC分类号： H05K7/00
CPC分类号： H05K3/4611 , H01L2224/16225 , H01L2924/15311 , H05K1/024 , H05K1/112 , H05K1/147 , H05K3/0064 , H05K3/4084 , H05K2201/091 , H05K2201/09318 , H05K2201/10734 , Y10T29/49126
摘要： A circuit board may include first and second sides, a plurality of circuit board layers between the sides, and a plurality of signal traces located in respective circuit board layers. The circuit board layers and the signal traces may extend from a first component connection region at the first side of the circuit board to a second component connection region at the first side of the circuit board. The signal traces may thus form stubless signal paths through the circuit board between the component connection regions. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
摘要翻译：电路板可以包括第一和第二侧，在侧面之间的多个电路板层和位于相应的电路板层中的多个信号迹线。电路板层和信号迹线可以从电路板的第一侧的第一部件连接区域延伸到电路板的第一侧的第二部件连接区域。因此，信号迹线可以在组件连接区域之间形成通过电路板的不连续的信号路径。当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明申请

US20080238588A1 Programmable passive equalizer 失效
标题翻译：可编程无源均衡器
公开(公告)号：US20080238588A1
公开(公告)日：2008-10-02
申请号：US12156532
申请日：2008-06-02
申请人： Evelina F. Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
发明人： Evelina F. Yeung , Sanjay Dabral , Pascal Meier , Santanu Chaudhuri
IPC分类号： H04B3/14
CPC分类号： H04B3/145
摘要： Embodiments of a programmable passive equalizer are described herein.
摘要翻译：本文描述了可编程无源均衡器的实施例。

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