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71. 发明申请

US20120315732A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND DEVICE USING SAME 有权
标题翻译：用于制造半导体器件的方法和使用其的器件
公开(公告)号：US20120315732A1
公开(公告)日：2012-12-13
申请号：US13438250
申请日：2012-04-03
申请人： Bo-Kyeong Kang , Jae-Seok Kim , Ho-Young Kim , Bo-Un Yoon , Il-Young Yoon
发明人： Bo-Kyeong Kang , Jae-Seok Kim , Ho-Young Kim , Bo-Un Yoon , Il-Young Yoon
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L21/823431 , H01L21/845
摘要： In a method for fabricating a semiconductor device, a substrate may be provided that includes: a base, an active fin that projects from an upper surface of the base and is integrally formed with the base, and a buffer oxide film pattern formed on the active fin in contact with the active fin. A first dummy gate film may be formed on the substrate to cover the buffer oxide film pattern and the first dummy gate film may be smoothed to expose the buffer oxide film pattern. A second dummy gate film may be formed on the exposed buffer oxide film pattern and the first dummy gate film.
摘要翻译：在制造半导体器件的方法中，可以提供一种基板，其包括：底座，从基座的上表面突出并与基座一体形成的活动翅片，以及形成在活动件上的缓冲氧化膜图案翅片与活动翅片接触。可以在衬底上形成第一伪栅极膜以覆盖缓冲氧化膜图案，并且可以平滑第一伪栅极膜以暴露缓冲氧化膜图案。可以在暴露的缓冲氧化膜图案和第一伪栅极膜上形成第二伪栅极膜。

72. 发明申请

US20120309189A1 METHODS FOR FABRICATING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120309189A1
公开(公告)日：2012-12-06
申请号：US13444175
申请日：2012-04-11
申请人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Yoon-Hae Kim , Doo-Sung Yun
发明人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Yoon-Hae Kim , Doo-Sung Yun
IPC分类号： H01L21/768
CPC分类号： H01L21/31144 , H01L21/76804 , H01L21/76808 , H01L21/76811 , H01L21/76877
摘要： In a method for fabricating a semiconductor device, a semiconductor device is provided including an interlayer dielectric film and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric film through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric film and the first and second hard mask patterns to fill the first trench. First and second hard mask trimming patterns are formed by trimming sidewalls of the first and second hard mask patterns and removing the filler material to expose the first trench. A damascene wire is formed by filling the first trench with a conductive material.
摘要翻译：在制造半导体器件的方法中，提供了半导体器件，其包括层间绝缘膜和顺序堆叠在其上的第一和第二硬掩模图案。第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间电介质膜中。在层间电介质膜和第一和第二硬掩模图案上设置填充材料以填充第一沟槽。通过修剪第一和第二硬掩模图案的侧壁并去除填充材料以暴露第一沟槽而形成第一和第二硬掩模修剪图案。通过用导电材料填充第一沟槽来形成镶嵌线。

73. 发明申请

US20120112317A1 INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS 有权
标题翻译：集成电路电容器具有支持端口
公开(公告)号：US20120112317A1
公开(公告)日：2012-05-10
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

74. 发明申请

US20120104514A1 Semiconductor Devices and Methods of Manufacturing the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120104514A1
公开(公告)日：2012-05-03
申请号：US13241324
申请日：2011-09-23
申请人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Myung-Geun Song
发明人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Myung-Geun Song
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/28518 , H01L21/76802 , H01L29/4175 , H01L29/41775 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7834 , H01L29/7845 , H01L29/7848
摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
摘要翻译：提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

75. 发明申请

US20120049250A1 Semiconductor Integrated Circuit Device Including an Epitaxial Layer 审中-公开
标题翻译：包括外延层的半导体集成电路器件
公开(公告)号：US20120049250A1
公开(公告)日：2012-03-01
申请号：US13191055
申请日：2011-07-26
申请人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sang-Jine Park , Bo-Un Yoon , Jeong-Nam Han , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： A semiconductor integrated circuit device includes a substrate. A gate structure is formed on the substrate and includes a gate insulating film and a gate electrode. A first sidewall spacer is formed on two sidewalls of the gate structure. A second sidewall spacer is formed on the first sidewall spacer. A recess compensation film is interposed between the second sidewall spacer and the substrate. An epitaxial layer is in contact with the recess compensation film.
摘要翻译：半导体集成电路器件包括衬底。栅极结构形成在衬底上并且包括栅极绝缘膜和栅电极。第一侧壁间隔件形成在栅极结构的两个侧壁上。在第一侧壁间隔件上形成第二侧壁间隔物。在第二侧壁间隔件和基板之间设置凹陷补偿膜。外延层与凹部补偿膜接触。

76. 发明申请

US20110306208A1 Method for Fabricating Semiconductor Device 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20110306208A1
公开(公告)日：2011-12-15
申请号：US13157393
申请日：2011-06-10
申请人： Jung-Won Lee , Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee
发明人： Jung-Won Lee , Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L21/28
CPC分类号： H01L28/91
摘要： Methods for forming a mold for a storage electrode in a semiconductor device include forming an interlayer dielectric layer including a contact plug on a substrate. A first mold dielectric layer is formed of a first material on the interlayer dielectric layer. A second mold dielectric layer is formed of a second material on the first mold dielectric layer. The second material has a different etch selectivity than the first material. A first opening is formed that penetrates the first and second mold dielectric layers. The first opening is dry etched to define a second opening having a larger width in the first mold dielectric layer than in the second mold dielectric layer based on the different etch selectivity of the first and second mold dielectric layers to define the mold for the storage electrode.
摘要翻译：在半导体器件中形成用于存储电极的模具的方法包括在衬底上形成包括接触插塞的层间介电层。第一模具电介质层由层间电介质层上的第一材料形成。第二模具电介质层由第一模具电介质层上的第二材料形成。第二种材料具有与第一种材料不同的蚀刻选择性。形成穿过第一和第二模具电介质层的第一开口。基于第一和第二模具电介质层的不同蚀刻选择性来限定用于存储电极的模具，第一开口被干蚀刻以限定在第一模具电介质层中具有比在第二模具电介质层中更大的宽度的第二开口。

77. 发明申请

US20110281415A1 METHODS OF FORMING AN ISOLATION LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING AN ISOLATION LAYER 失效
标题翻译：形成隔离层的方法和制造具有隔离层的半导体器件的方法
公开(公告)号：US20110281415A1
公开(公告)日：2011-11-17
申请号：US13109527
申请日：2011-05-17
申请人： Dae-Hyuk KANG , Jung-Won Lee , Bo-Un Yoon , Kun-Tack Lee
发明人： Dae-Hyuk KANG , Jung-Won Lee , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/76229 , H01L21/28273 , H01L27/11526 , H01L27/11531
摘要： In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
摘要翻译：在形成隔离层的方法中，在衬底上形成第一和第二沟槽。第一和第二沟槽分别具有第一宽度和第二宽度，第二宽度大于第一宽度。第二隔离层图案部分地填充第二沟槽。形成第一隔离层图案和第三隔离层图案。第一隔离层图案填充第一沟槽，并且第三隔离层图案形成在第二隔离层图案上并且填充第二沟槽的剩余部分。

78. 发明授权

US08038508B2 Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
标题翻译：用于抛光晶片的装置和用于检测抛光终点的方法
公开(公告)号：US08038508B2
公开(公告)日：2011-10-18
申请号：US12285852
申请日：2008-10-15
申请人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
发明人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
IPC分类号： B24B49/00
CPC分类号： B24B9/065 , B24B21/02 , B24B37/013 , B24B49/12
摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
摘要翻译：晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。

79. 发明授权

US08008172B2 Methods of forming semiconductor devices including multistage planarization and crystalization of a semiconductor layer 有权
标题翻译：形成半导体器件的方法包括半平面化和半导体层的结晶化
公开(公告)号：US08008172B2
公开(公告)日：2011-08-30
申请号：US12070220
申请日：2008-02-15
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/20 , H01L21/36 , H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76229 , H01L21/3212
摘要： A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。

80. 发明申请

US20110100693A1 LOW-RESISTANCE CONDUCTIVE PATTERN STRUCTURES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：低电阻导电图案结构及其制作方法
公开(公告)号：US20110100693A1
公开(公告)日：2011-05-05
申请号：US12910356
申请日：2010-10-22
申请人： Byoung-Ho Kwon , Bo-Un Yoon
发明人： Byoung-Ho Kwon , Bo-Un Yoon
IPC分类号： H05K1/18 , H05K1/02
CPC分类号： H01L23/528 , H01L21/76807 , H01L21/76816 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A conductive structure includes a contact plug extending through an insulating layer on a substrate, and first and second conductive lines extending alongside one another on the insulating layer. The first conductive line extends on the contact plug. A connecting line on the insulating layer extends between and electrically connects the first and second conductive lines. Related integrated circuit devices and fabrication methods are also discussed.
摘要翻译：导电结构包括延伸穿过衬底上的绝缘层的接触插塞以及在绝缘层上彼此并排延伸的第一和第二导电线。第一导线延伸在接触插头上。绝缘层上的连接线在第一和第二导电线之间延伸并电连接。还讨论了相关的集成电路器件和制造方法。

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