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71. 发明申请

US20050247987A1 Flash memory device and method for fabricating the same 失效
标题翻译：闪存装置及其制造方法
公开(公告)号：US20050247987A1
公开(公告)日：2005-11-10
申请号：US11121495
申请日：2005-05-03
申请人： Sang Lee
发明人： Sang Lee
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , Y10S438/954
摘要： A flash memory device and a method for fabricating the same is disclosed that reduces or prevents mis-operation and improves integration, which includes a semiconductor substrate having a field region and an active region; a device isolation layer on the field region including a conductive (e.g., polysilicon) layer and an insulating layer thereon; a sidewall spacer at sides of the device isolation layer; an ONO layer on the active region; a gate electrode on the ONO layer; source and drain regions at sides of the gate electrode in the active region; a passivation layer on the semiconductor substrate, having a contact hole in the drain region; and a drain electrode in the contact hole, connected with the drain region.
摘要翻译：公开了一种闪存器件及其制造方法，其减少或防止错误操作和改进集成，其包括具有场区域和有源区域的半导体衬底; 在场区域上的器件隔离层，包括导电（例如多晶硅）层和绝缘层; 在所述器件隔离层的侧面处的侧壁间隔物; 活性区上的ONO层; ONO层上的栅电极; 源极和漏极区域在栅电极的有源区中; 半导体衬底上的钝化层，在漏区中具有接触孔; 和接触孔中的漏电极，与漏区连接。

72. 发明申请

US20050247973A1 Nonvolatile memory device and method for fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20050247973A1
公开(公告)日：2005-11-10
申请号：US11121866
申请日：2005-05-03
申请人： Sang Lee
发明人： Sang Lee
IPC分类号： H01L21/76 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42336 , H01L29/7885
摘要： A nonvolatile memory device and a method for fabricating the same is disclosed, in which a corner of a floating gate is rounded to reduce, minimize or prevent discharge of programmed electrons, and an overlap between the floating gate and a control gate increases to improve a coupling ratio and enable nonvolatile memory device operations at a low voltage. The nonvolatile memory device includes a device isolation layer in a field region on a semiconductor substrate, the device isolation having a trench; a tunnel oxide layer; a floating gate comprising a polysilicon pattern in an active region of the semiconductor substrate and a polysilicon spacer at the side of the polysilicon pattern and the inner sidewall of the trench; a gate dielectric layer on the floating gate; and a control gate on the gate dielectric layer overlapping with the floating gate.
摘要翻译：公开了一种非易失性存储器件及其制造方法，其中浮动栅极的角被倒圆以减少，最小化或防止编程电子的放电，并且浮置栅极和控制栅极之间的重叠增加以改善耦合比，并使得非易失性存储器件在低电压下工作。非易失性存储器件包括在半导体衬底上的场区中的器件隔离层，器件隔离具有沟槽; 隧道氧化层; 包括在所述半导体衬底的有源区域中的多晶硅图案的浮置栅极和在所述多晶硅图案侧和所述沟槽的内侧壁处的多晶硅间隔物; 浮栅上的栅介质层; 并且栅极电介质层上的与浮动栅极重叠的控制栅极。

73. 发明申请

US20050239825A1 Modulation of inflammatory and metastatic processes 有权
标题翻译：调节炎症和转移过程
公开(公告)号：US20050239825A1
公开(公告)日：2005-10-27
申请号：US11061386
申请日：2005-02-18
申请人： Carla Heise , Sang Lee
发明人： Carla Heise , Sang Lee
IPC分类号： A61K31/4709 , A61K31/497 , A61K31/5377
CPC分类号： A61K31/497 , A61K31/4709 , A61K31/5377
摘要： Methods of using compounds having Structure I or the salts or tautomers of the compounds in the treatment of disorders relating to cell adhesion and metastatic processes are presented herein.
摘要翻译：本文提供了使用具有结构I的化合物或化合物的盐或互变异构体的治疗与细胞粘附和转移过程相关的疾病的方法。

74. 发明申请

US20050238574A1 High performance water gas shift catalyst and a method of preparing the same 审中-公开
标题翻译：高性能水煤气变换催化剂及其制备方法
公开(公告)号：US20050238574A1
公开(公告)日：2005-10-27
申请号：US10852452
申请日：2004-05-25
申请人： Dong Moon , Jong Ryu , Dae Kim , Sang Lee , Byung Lee
发明人： Dong Moon , Jong Ryu , Dae Kim , Sang Lee , Byung Lee
IPC分类号： B01J23/63 , B01J23/89 , B01J37/02 , C01B3/16 , C01B3/26
CPC分类号： B01J37/0201 , B01J23/894 , B01J37/0207 , C01B3/16 , C01B2203/0283 , C01B2203/1058 , C01B2203/107 , C01B2203/1076 , C01B2203/1082 , Y02P20/52
摘要： The present invention relates to a high performance water gas shift catalyst and a method of preparing the same, more particularly to a high performance water gas shift catalyst comprising active components such as copper (Cu), nickel (Ni) and platinum (Pt) and a ceria (CeO2) support, which has better catalytic activity and thermal cycling durability with minimum platinum supporting amount of 1 wt % or less compared with the conventional Pt/CeO2 catalyst and LTS catalyst, and a method of preparing the same.
摘要翻译：本发明涉及一种高性能水煤气变换催化剂及其制备方法，更具体地涉及包含有效成分如铜（Cu），镍（Ni）和铂（Pt）的高性能水煤气变换催化剂和具有较好的催化活性和热循环耐久性的二氧化铈（CeO 2 2）载体，与常规的Pt / CeO 2 2相比，铂载体的最小铂负载量为1重量％以下。催化剂和LTS催化剂及其制备方法。

75. 发明申请

US20050226090A1 Pseudo SRAM having combined synchronous and asynchronous mode register set 有权
标题翻译：具有组合同步和异步模式寄存器组的伪SRAM
公开(公告)号：US20050226090A1
公开(公告)日：2005-10-13
申请号：US10878326
申请日：2004-06-29
申请人： Sang Lee
发明人： Sang Lee
IPC分类号： G11C11/408 , G11C5/00 , G11C7/10 , G11C11/403 , G11C11/406 , G11C11/4193
CPC分类号： G11C11/40615 , G11C7/1045 , G11C11/406
摘要： A PSRAM features a mode register set (MRS) for setting a mode register at a combined synchronous and asynchronous mode. The PSRAM having a combined synchronous and asynchronous mode register set includes a MRS, a mode register control unit, a plurality of control signal buffers, an address buffer, a clock buffer, and a synchronous and asynchronous detecting unit. Here, the plurality of control signal buffers, the address buffer and the clock buffers are controlled by a chip selecting signal at an asynchronous mode, and are operated synchronously with respect to an internal clock outputted from the clock buffer regardless of the chip selecting signal at a synchronous mode.
摘要翻译： PSRAM具有用于在组合同步和异步模式下设置模式寄存器的模式寄存器集（MRS）。具有组合同步和异步模式寄存器集的PSRAM包括MRS，模式寄存器控制单元，多个控制信号缓冲器，地址缓冲器，时钟缓冲器和同步和异步检测单元。这里，多个控制信号缓冲器，地址缓冲器和时钟缓冲器由异步模式下的芯片选择信号控制，并且相对于从时钟缓冲器输出的内部时钟同步地操作，而与芯片选择信号无关同步模式。

76. 发明申请

US20050208700A1 Die to substrate attach using printed adhesive 审中-公开
标题翻译：使用印刷胶粘剂粘附到基材上
公开(公告)号：US20050208700A1
公开(公告)日：2005-09-22
申请号：US10966572
申请日：2004-10-15
申请人： Hyeog Kwon , Sang Lee , Jong Ju
发明人： Hyeog Kwon , Sang Lee , Jong Ju
IPC分类号： H01L21/48 , H01L21/50 , H01L21/58 , H01L25/065
CPC分类号： H01L24/27 , H01L24/29 , H01L24/45 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2224/83192 , H01L2224/83193 , H01L2224/83856 , H01L2225/0651 , H01L2225/06568 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01079 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor chip packaging method (34) includes printing an adhesive (46) on a support surface (42), typically a surface of a semiconductor substrate (44), to create individual adhesive areas (40). Semiconductor chips (24) are individually placed on the individual adhesive areas thereby securing the semiconductor chips to the support surface to create first chip subassemblies (55). The semiconductor chip and the semiconductor substrate are electrically connected to create second chip subassemblies (62). At least a portion of each of at least some of the second chip subassemblies is encapsulated to create semiconductor chip packages (64). The adhesive at the individual adhesive areas is preferably a B-staged adhesive so that solvent is removed from the adhesive before the individually placing step.
摘要翻译：半导体芯片封装方法（34）包括将粘合剂（46）印刷在支撑表面（42）上，通常是半导体衬底（44）的表面，以形成单独的粘合区域（40）。半导体芯片（24）被分别放置在各个粘合区域上，从而将半导体芯片固定到支撑表面以形成第一芯片子组件（55）。半导体芯片和半导体衬底被电连接以形成第二芯片子组件（62）。至少部分第二芯片组件的至少一部分被封装以形成半导体芯片封装（64）。单个粘合剂区域处的粘合剂优选为B级粘合剂，使得在单独放置步骤之前将溶剂从粘合剂中除去。

77. 发明申请

US20050201167A1 PSRAM for performing write-verify-read function 失效
标题翻译： PSRAM用于执行写入验证读取功能
公开(公告)号：US20050201167A1
公开(公告)日：2005-09-15
申请号：US10876778
申请日：2004-06-28
申请人： Sang Lee , Tae Kwon
发明人： Sang Lee , Tae Kwon
IPC分类号： G11C11/4193 , G11C7/00
CPC分类号： G11C11/40615 , G11C8/10 , G11C11/401 , G11C29/50016
摘要： A PSRAM performs a Write-Verify-Read function at a test mode, thereby easily analyzing defects. The PSRAM comprises a test mode decoder, a refresh control block and a precharge control block. The test mode decoder generates a test mode control signal for performing a WVR function when a test mode starts. The refresh control block selectively performs a refresh operation in response to the test mode control signal. The precharge control block selectively performs a precharge operation in response to the test mode control signal outputted from the test mode decoder. Here, the test mode control signal is activated at the test mode so that the refresh operation and the precharge operation are not performed.
摘要翻译： PSRAM在测试模式下执行写入验证读取功能，从而轻松分析缺陷。 PSRAM包括测试模式解码器，刷新控制块和预充电控制块。当测试模式开始时，测试模式解码器产生用于执行WVR功能的测试模式控制信号。刷新控制块根据测试模式控制信号有选择地执行刷新操作。预充电控制块响应于从测试模式解码器输出的测试模式控制信号选择性地执行预充电操作。这里，在测试模式下激活测试模式控制信号，使得不执行刷新操作和预充电操作。

78. 发明申请

US20050188405A1 System and method of providing integrated communications and broadcasting service 审中-公开
标题翻译：提供综合通信和广播业务的系统和方法
公开(公告)号：US20050188405A1
公开(公告)日：2005-08-25
申请号：US11008321
申请日：2004-12-08
申请人： Kang Lee , Sang Lee , Heyung Lee , Kwang Cho , Bong Kim
发明人： Kang Lee , Sang Lee , Heyung Lee , Kwang Cho , Bong Kim
IPC分类号： H04N7/22 , H04B10/00 , H04B10/27 , H04B10/272 , H04J14/00 , H04J14/02 , H04L12/28 , H04N7/10 , H04N21/61 , H04N21/647 , H04N7/173 , H04N7/16 , H04N7/20
CPC分类号： H04N7/16 , H04H20/76 , H04N7/17309 , H04N7/22 , H04N21/2665 , H04N21/6118 , H04N21/6187
摘要： A system for and a method of providing an integrated communications and broadcasting service are provided. This system includes a transmitter and a receiver. The transmitter RF-multiplexes a CATV broadcasting signal and a satellite broadcasting signal, converts the RF-multiplexed broadcasting signal into an RF-multiplexed broadcasting optical signal having a predetermined wavelength, multiplexes the broadcasting optical signal with an Internet data signal, and transmits an integrated communications and broadcasting optical signal via a predetermined optical fiber. The receiver receives the integrated communications and broadcasting optical signal from the transmitter, demultiplexes the received signal according to a wavelength band to separate the received signal into the broadcasting optical signal and the Internet data signal, separates the broadcasting optical signal into the CATV broadcasting signal and the satellite broadcasting signal using the difference between wavelength bands of the CATV broadcasting signal and the satellite broadcasting signal, and transports the separated signals to appropriate terminals.
摘要翻译：提供了一种提供集成通信和广播服务的系统和方法。该系统包括发射机和接收机。发射机对CATV广播信号和卫星广播信号进行RF复用，将RF多路复用广播信号转换为具有预定波长的RF多路复用广播光信号，将广播光信号与因特网数据信号进行多路复用，并发送集成通过预定的光纤通信和广播光信号。接收机接收来自发射机的集成通信和广播光信号，根据波段分解接收到的信号，将接收到的信号分离成广播光信号和因特网数据信号，将广播光信号分离成CATV广播信号，使用CATV广播信号的波段和卫星广播信号之间的差的卫星广播信号，并将分离的信号传送到适当的终端。

79. 发明申请

US20050156682A1 Voltage-controlled oscillator using current feedback network 有权
标题翻译：使用电流反馈网络的压控振荡器
公开(公告)号：US20050156682A1
公开(公告)日：2005-07-21
申请号：US10957749
申请日：2004-10-05
申请人： Ja Lee , Sang Lee , Jin Kang , Seung Oh
发明人： Ja Lee , Sang Lee , Jin Kang , Seung Oh
IPC分类号： H03B5/08 , H03B1/00 , H03B5/12
CPC分类号： H03B5/1231 , H03B5/1215 , H03B5/1221 , H03B5/1243
摘要： Provided is a voltage-controlled oscillator (VCO) using a current feedback network for use in a wireless communication terminal. The voltage-controlled oscillator has high input impedance and low output impedance, so that a degree of isolation from the external load is excellent, thereby preventing degradation of the Q-factor by the load in overall oscillation circuit. In the voltage-controlled oscillator of the present invention, an LC resonator is provided to generate positive feedback, and negative resistance may be obtained at a wider frequency range by tuning a varactor of the LC resonator. And a boosting inductor is inserted into the positive feedback loop to have a greater negative resistance, therefore it is possible to prevent a problem in which the oscillation does not occur due to the parasitic resistance components generated during circuit fabrication.
摘要翻译：提供了一种使用电流反馈网络在无线通信终端中使用的压控振荡器（VCO）。压控振荡器具有高输入阻抗和低输出阻抗，使得与外部负载的隔离度优异，从而防止整个振荡电路中的负载对Q因子的劣化。在本发明的压控振荡器中，设置LC谐振器以产生正反馈，并且通过调谐LC谐振器的变容二极管可以在更宽的频率范围内获得负电阻。并且将增压电感器插入到正反馈回路中以具有更大的负电阻，因此可以防止由于在电路制造期间产生的寄生电阻分量而不发生振荡的问题。

80. 发明申请

US20050153493A1 Method for forming dual gate electrodes using damascene gate process 失效
标题翻译：使用镶嵌门工艺形成双栅电极的方法
公开(公告)号：US20050153493A1
公开(公告)日：2005-07-14
申请号：US11017762
申请日：2004-12-22
申请人： Sang Lee
发明人： Sang Lee
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/78 , H01L21/337
CPC分类号： H01L21/28202 , H01L21/82345 , H01L21/823462 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for forming dual gate electrodes using a damascene gate process is disclosed. A disclosed method comprises: growing a first gate oxide layer on a semiconductor substrate; performing a thermal treatment for a first gate oxide layer; removing a predetermined part of the first gate oxide layer until the top surface of the semiconductor substrate is exposed; growing a second gate oxide layer as a thin oxide layer on the exposed semiconductor substrate, thereby making the first gate oxide layer as a thick oxide layer; depositing polysilicon on the entire surface of the semiconductor substrate and forming dummy gates through a photolithography and an etching processes; forming sidewall spacers on the lateral faces of the dummy gates; forming source and drain regions in the substrate under both sides of the dummy gates; removing the dummy gates and the second gate oxide layer; forming an insulating layer where the second gate oxide layer is removed; performing a thermal treatment for the insulating layer; filling polysilicon for gate electrodes where the dummy gates were removed; and planarizing the resulting structure until the gate electrodes are exposed.
摘要翻译：公开了一种使用镶嵌门工艺形成双栅电极的方法。所公开的方法包括：在半导体衬底上生长第一栅极氧化物层; 对第一栅极氧化物层进行热处理; 去除第一栅极氧化物层的预定部分直到半导体衬底的顶表面露出; 在暴露的半导体衬底上生长第二栅极氧化物层作为薄氧化物层，从而使第一栅氧化层作为厚氧化物层; 在半导体衬底的整个表面上沉积多晶硅，并通过光刻和蚀刻工艺形成伪栅极; 在所述伪栅极的侧面上形成侧壁间隔物; 在所述虚拟栅极的两侧形成在所述衬底中的源区和漏区; 去除伪栅极和第二栅极氧化物层; 形成除去第二栅极氧化物层的绝缘层; 对绝缘层进行热处理; 为去除虚拟栅极的栅电极填充多晶硅; 并平坦化所得到的结构，直到栅电极露出。

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