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71. 发明申请

US20050204237A1 Method and system for providing interactive testing of integrated circuits 失效
标题翻译：提供集成电路交互式测试的方法和系统
公开(公告)号：US20050204237A1
公开(公告)日：2005-09-15
申请号：US10789710
申请日：2004-02-27
申请人： Todd Burdine , Franco Motika , Peilin Song
发明人： Todd Burdine , Franco Motika , Peilin Song
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/261 , G01R31/31703 , G01R31/318371 , G06F11/263
摘要： A method for providing interactive and iterative testing of integrated circuits including the receiving of a first failing region. The first failing region corresponds to one or more circuits on the integrated circuit. The method generates a set of adaptive algorithmic test patterns for the one or more circuits in response to the first failing region and to a logic model of the integrated circuit. Expected results for the test patterns are determined. The method includes applying the test patterns to the first failing region on the integrated circuit resulting in actual results for the test patterns. The expected results to the actual results are compared. The method also transmits mismatches between the expected results and the actual results to a fault simulator. The method includes receiving a second failing region from the fault simulator, the second failing region created in response to the mismatches and the logic model, and the second failing region corresponding to a subset of the one or more circuits on the integrated circuit.
摘要翻译：一种用于提供集成电路的交互式和迭代测试的方法，包括接收第一故障区域。第一故障区域对应于集成电路上的一个或多个电路。该方法响应于第一故障区域和集成电路的逻辑模型生成针对一个或多个电路的一组自适应算法测试模式。确定测试模式的预期结果。该方法包括将测试图案应用于集成电路上的第一故障区域，从而得到测试图案的实际结果。对实际结果的预期结果进行比较。该方法还将预期结果与实际结果之间的错配传输到故障模拟器。该方法包括从故障模拟器接收第二故障区域，响应于不匹配和逻辑模型而创建的第二故障区域，以及对应于集成电路上的一个或多个电路的子集的第二故障区域。

72. 发明授权

US06516432B1 AC scan diagnostic method 失效
标题翻译： AC扫描诊断方法
公开(公告)号：US06516432B1
公开(公告)日：2003-02-04
申请号：US09469699
申请日：1999-12-22
申请人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
发明人： Franco Motika , Phillip J. Nigh , Peilin Song , Howard B. Druckerman
IPC分类号： G01R3128
CPC分类号： G01R31/318577
摘要： Disclosed is an alternating current (AC) scan diagnostic system in which one or a plurality of scan chains are tested by serially propagating predetermined bit patterns through the scan chain and comparing the output against an expected result. The system comprises identification phase, verifications and localization, and a characterization phases. The system is adaptable for use with on-board diagnostics and is adaptable for use with on-product clock generation systems.
摘要翻译：公开了一种交流（AC）扫描诊断系统，其中一个或多个扫描链通过通过扫描链串行传播预定位图案并将输出与预期结果进行比较来测试。该系统包括识别阶段，验证和定位以及特征化阶段。该系统适用于车载诊断，适用于产品上的时钟发生系统。

73. 发明授权

US09069989B2 Chip authentication using scan chains 有权
标题翻译：使用扫描链的芯片认证
公开(公告)号：US09069989B2
公开(公告)日：2015-06-30
申请号：US13360267
申请日：2012-01-27
申请人： Franco Motika , Dirk Pfeiffer , Peilin Song
发明人： Franco Motika , Dirk Pfeiffer , Peilin Song
IPC分类号： G06F21/73 , G01R31/3185 , G01R31/3183 , G06F7/58
CPC分类号： G01R31/3177 , G01R31/318328 , G01R31/318541 , G01R31/318547 , G06F7/588 , G06F21/73
摘要： Methods and systems for generating a circuit identification number include determining a propagation time delay across a scan chain of known length; comparing the propagation time delay to a threshold associated with the scan chain length; storing an identifier bit based on the result of the comparison; repeating the steps of determining, comparing, and storing until a number of stored identifier bits reaches a threshold number; and outputting the stored identifier bits.
摘要翻译：用于产生电路识别号码的方法和系统包括确定跨越已知长度的扫描链的传播时间延迟; 将传播时间延迟与扫描链长度相关联的阈值进行比较; 基于比较结果存储标识符位; 重复确定，比较和存储的步骤，直到多个存储的标识符比特达到阈值数; 并输出所存储的标识符位。

74. 发明授权

US07826045B2 Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效
标题翻译：用于电路分析的固体浸液显微镜中的角度光谱裁剪
公开(公告)号：US07826045B2
公开(公告)日：2010-11-02
申请号：US12020157
申请日：2008-01-25
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：一种用于定位半导体芯片中的故障的方法和结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

75. 发明授权

US07010735B2 Stuck-at fault scan chain diagnostic method 失效
标题翻译：堵塞故障扫描链诊断方法
公开(公告)号：US07010735B2
公开(公告)日：2006-03-07
申请号：US10043486
申请日：2002-01-10
申请人： Franco Motika , Philip J. Nigh , Peilin Song
发明人： Franco Motika , Philip J. Nigh , Peilin Song
IPC分类号： G01R31/28
CPC分类号： G11C29/025 , G01R31/318342 , G11C29/02 , G11C29/32
摘要： While data cannot be transmitted down a scan chain through a stuck-at fault location, data in properly operating latches downstream of the stuck-at fault location can be shifted down the chain. By varying operating parameters, such as power supply and reference voltages, clock timing patterns, temperature and timing sequences, one or more latches down the SRL chain from the stuck-at fault location may be triggered to change state from the stuck-at fault value. The SRL chain is then operated to shift data out the output of the SRL chain. The output is monitored and any change in value from the stuck-at state is noted as identifying all good latch positions to end of the chain. The process is repeated: varying each of the selected operating parameters until the latch position following the stuck-at fault latch is identified.
摘要翻译：虽然数据不能通过卡住的故障位置沿扫描链传输，但在卡住故障位置下游的正确操作的锁存器中的数据可以向下移动。通过改变操作参数，例如电源和参考电压，时钟时序模式，温度和时序，可以触发从链路故障位置向下链接的一个或多个锁存器，以将状态从卡入故障值。然后运行SRL链将数据移出SRL链的输出。输出被监视，并且从卡入状态的值的任何变化被注意为将所有良好的锁定位置识别到链的末端。重复该过程：改变所选择的每个操作参数，直到识别出卡入故障锁存之后的锁存位置。

76. 发明申请

US20050116759A1 Programmable jitter signal generator 有权
标题翻译：可编程抖动信号发生器
公开(公告)号：US20050116759A1
公开(公告)日：2005-06-02
申请号：US10725847
申请日：2003-12-02
申请人： Keith Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
发明人： Keith Jenkins , Jien-Chung Lo , Peilin Song , Tian Xia
IPC分类号： G01R31/317 , G06F1/03 , G06F1/04 , H03K5/00 , H03K5/13 , H03K5/15
CPC分类号： G01R31/31709 , G01R31/31727 , G06F1/03 , H03K5/133 , H03K5/1506 , H03K2005/00058
摘要： A programmable jitter signal generator is provided that includes a jitter distribution control unit, a selection unit in signal communication with the jitter distribution control unit, and a delay unit in signal communication with the selection unit; and a corresponding method of generating a programmable jitter signal includes programming a control unit, receiving a reference signal, delaying the received reference signal by a multiple of a base time increment, and selecting a delayed reference signal delayed by a desired multiple of the base time increment in accordance with the programmed control unit.
摘要翻译：提供了一种可编程抖动信号发生器，其包括抖动分布控制单元，与抖动分布控制单元进行信号通信的选择单元，以及与选择单元进行信号通信的延迟单元; 并且产生可编程抖动信号的相应方法包括编程控制单元，接收参考信号，将接收到的参考信号延迟基准时间增量的倍数，以及选择延迟基准时间的期望倍数的延迟参考信号根据编程的控制单元增量。

77. 发明授权

US06728914B2 Random path delay testing methodology 有权
标题翻译：随机路径延迟测试方法
公开(公告)号：US06728914B2
公开(公告)日：2004-04-27
申请号：US09745603
申请日：2000-12-22
申请人： Kevin William McCauley , William Vincent Huott , Mary Prilotski Kusko , Peilin Song , Richard Frank Rizzolo , Ulrich Baur , Franco Motika
发明人： Kevin William McCauley , William Vincent Huott , Mary Prilotski Kusko , Peilin Song , Richard Frank Rizzolo , Ulrich Baur , Franco Motika
IPC分类号： G01R3128
CPC分类号： G01R31/318385 , G01R31/31858
摘要： For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.
摘要翻译：对于逻辑电路中的每个逻辑门，确定包含门的所有路径，并且通过其每个输入或启动SRL和每个输出或捕获SRL之间的长度对路径进行分类。路径被分配单个阈值，然后根据它们相对于阈值的路径长度分类被分成两组，每组中的所有路径被视为单个路径。然后使用标准LBIST工具模拟伪随机LBIST图案。当与逻辑门相关联的故障由长度高于阈值的路径的捕获SRL检测到时，故障被视为测试并从故障列表中标记出来。当在低于阈值的任何路径中检测到故障时，它不会被标记，并且故障的测试继续进行，直到测试模式为低于阈值的组的所有路径。当组件的所有故障路径都低于阈值时，已经测试了单独确定的测试生成程序。在生成的测试中，故障被迫通过超过阈值的最长路径传播。

78. 发明授权

US06490702B1 Scan structure for improving transition fault coverage and scan diagnostics 失效
标题翻译：用于改善过渡故障覆盖和扫描诊断的扫描结构
公开(公告)号：US06490702B1
公开(公告)日：2002-12-03
申请号：US09473810
申请日：1999-12-28
申请人： Peilin Song , Richard F. Rizzolo , Franco Motika , Ulrich W. Baur
发明人： Peilin Song , Richard F. Rizzolo , Franco Motika , Ulrich W. Baur
IPC分类号： G01R3128
CPC分类号： G01R31/318541
摘要： A scan chain latch circuit is provided. The scan chain latch circuit includes a first shift register latch and a second shift register latch. The scan chain latch circuit also includes a multiplexor connected between the first and second shift register latches, the multiplexor has a select line for controlling the function of the multiplexor. The multiplexor is configured for implementing an inverting mode such that a logic value may be passed via the multiplexor from the first shift register latch to the second shift register latch in one of a non-inverted state and an inverted state based upon the state of the select line.
摘要翻译：提供扫描链锁存电路。扫描链锁存电路包括第一移位寄存器锁存器和第二移位寄存器锁存器。扫描链锁存电路还包括连接在第一和第二移位寄存器锁存器之间的多路复用器，多路复用器具有用于控制多路复用器功能的选择线。多路复用器被配置为实现反相模式，使得逻辑值可以以非反相状态和反相状态中的一个从第一移位寄存器锁存器传递到第二移位寄存器锁存器，基于选择行。

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