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71. 发明申请

US20050253575A1 Reliability evaluation test apparatus, reliability evaluation test system, contactor, and reliability evaluation test method 有权
标题翻译：可靠性评估试验装置，可靠性评价试验系统，接触器和可靠性评价试验方法
公开(公告)号：US20050253575A1
公开(公告)日：2005-11-17
申请号：US11179538
申请日：2005-07-13
申请人： Kiyoshi Takekoshi , Hisatomi Hosaka , Junichi Hagihara , Kunihiko Hatsushika , Takamasa Usui , Hisashi Kaneko , Nobuo Hayasaka , Yoshiyuki Ido
发明人： Kiyoshi Takekoshi , Hisatomi Hosaka , Junichi Hagihara , Kunihiko Hatsushika , Takamasa Usui , Hisashi Kaneko , Nobuo Hayasaka , Yoshiyuki Ido
IPC分类号： G01R31/26 , G01R1/04 , G01R31/28 , G01R31/30 , H01L21/66
CPC分类号： G01R31/2862 , G01R1/0433 , G01R1/0491 , G01R31/2831 , G01R31/286 , G01R31/2865 , G01R31/2867 , G01R31/287 , G01R31/2886
摘要： A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
摘要翻译：本发明的可靠性评价试验装置包括晶片存储部，其以形成在晶片上的多个器件的电极焊盘和接触器的凸块完全电接触的状态存储晶片。晶片存储部分向/从测量部分发送/接收测试信号，并具有密封和隔热结构。晶片存储部分具有压力接触器的压力机构和将与接触器完全接触的晶片直接加热到预定高温的加热机构。在加速条件下评估形成在半导体晶片上的互连膜和绝缘膜的可靠性。

72. 发明授权

US06730447B2 Manufacturing system in electronic devices 失效
标题翻译：电子设备制造系统
公开(公告)号：US06730447B2
公开(公告)日：2004-05-04
申请号：US10092486
申请日：2002-03-08
申请人： Shinichi Ito , Tatsuhiko Higashiki , Hiroshi Ikegami , Nobuo Hayasaka
发明人： Shinichi Ito , Tatsuhiko Higashiki , Hiroshi Ikegami , Nobuo Hayasaka
IPC分类号： G03C500
CPC分类号： G03F7/70633 , B23K26/04 , B23K26/042 , B23K2101/40 , G03F9/7076 , Y10S430/146 , Y10T29/413
摘要： A laser processing apparatus comprises a laser oscillator for producing a laser beam to selectively remove part of a substrate to be processed, a scanning system for applying the laser beam to an arbitrary position of the substrate and incident means for applying the laser beam to the substrate substantially at right angle.
摘要翻译：激光加工装置包括：激光振荡器，用于产生激光束以选择性地去除待处理的基板的一部分，用于将激光束施加到基板的任意位置的扫描系统和用于将激光束施加到基板的入射装置基本上是直角。

73. 发明授权

US06717251B2 Stacked type semiconductor device 有权
标题翻译：堆叠型半导体器件
公开(公告)号：US06717251B2
公开(公告)日：2004-04-06
申请号：US09961332
申请日：2001-09-25
申请人： Mie Matsuo , Nobuo Hayasaka , Tsunetoshi Arikado , Hidemi Ishiuchi , Koji Sakui , Chiaki Takubo
发明人： Mie Matsuo , Nobuo Hayasaka , Tsunetoshi Arikado , Hidemi Ishiuchi , Koji Sakui , Chiaki Takubo
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L25/0652 , H01L25/16 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06572 , H01L2225/06596 , H01L2924/00014 , H01L2924/1627 , H01L2224/0401
摘要： Provided is a stacked type semiconductor device formed of a plurality of semiconductor integrated circuit devices stacked, each having a specification and including a semiconductor integrated circuit chip, wherein at least three of the semiconductor integrated circuit devices are stacked in the order of a value of the specification.
摘要翻译：本发明提供一种层叠型半导体器件，其由堆叠的多个半导体集成电路器件形成，每个半导体集成电路器件具有规格并且包括半导体集成电路芯片，其中至少三个半导体集成电路器件按照规范。

74. 发明授权

US06657306B1 Paste including a mixture of powders, connection plug, burying method, and semiconductor device manufacturing method 失效
标题翻译：糊料包括粉末混合物，连接插头，埋入方法和半导体器件制造方法
公开(公告)号：US06657306B1
公开(公告)日：2003-12-02
申请号：US09722467
申请日：2000-11-28
申请人： Keiichi Sasaki , Manabu Kimura , Yoshimi Hisatsune , Nobuo Hayasaka
发明人： Keiichi Sasaki , Manabu Kimura , Yoshimi Hisatsune , Nobuo Hayasaka
IPC分类号： H01L2348
CPC分类号： H01L21/76898 , H01L21/288 , H01L21/76877 , H01L21/76882 , H01L23/481 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
摘要翻译：在半导体衬底的主表面上形成沟槽，然后在沟槽中埋设糊状物。糊状物含有具有导电物质和树脂的固体，以及用于溶解树脂的溶剂。糊剂的固体成分不小于60体积％，粘度比不大于2。

75. 发明授权

US06235624B1 Paste connection plug, burying method, and semiconductor device manufacturing method 失效
标题翻译：粘贴连接插头，埋入方法和半导体器件制造方法
公开(公告)号：US06235624B1
公开(公告)日：2001-05-22
申请号：US09321534
申请日：1999-05-28
申请人： Keiichi Sasaki , Manabu Kimura , Nobuo Hayasaka
发明人： Keiichi Sasaki , Manabu Kimura , Nobuo Hayasaka
IPC分类号： H01L214763
CPC分类号： H01L21/76898 , H01L21/288 , H01L21/76877 , H01L21/76882 , H01L23/481 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
摘要翻译：在半导体衬底的主表面上形成沟槽，然后在沟槽中埋设糊状物。糊状物含有具有导电物质和树脂的固体，以及用于溶解树脂的溶剂。糊剂的固体成分不小于60体积％，粘度比不大于2。

76. 发明授权

US6165617A Resin-coated copper foil for multilayer printed wiring board and multilayer printed wiring board provided with said copper foil 失效
标题翻译：用于多层印刷线路板的树脂涂覆铜箔和设置有所述铜箔的多层印刷线路板
公开(公告)号：US6165617A
公开(公告)日：2000-12-26
申请号：US981751
申请日：1997-12-31
申请人： Tetsurou Satoh , Hiroaki Tsuyoshi , Nobuo Hayasaka
发明人： Tetsurou Satoh , Hiroaki Tsuyoshi , Nobuo Hayasaka
IPC分类号： B32B15/08 , B32B15/20 , B32B27/38 , C08L63/00 , H05K3/38 , H05K3/46 , B32B15/04 , H05K1/02
CPC分类号： H05K3/386 , B32B15/08 , B32B15/20 , B32B27/38 , C08L63/00 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K2201/0133 , H05K2201/0355 , H05K2201/0358 , Y10T428/12903 , Y10T428/31529 , Y10T428/31605 , Y10T428/31678 , C08L75/04 , C08L2666/02 , C08L2666/08 , C08L2666/04
摘要： A resin-coated copper foil for use in a multilayer printed wiring board, characterized by having on one surface thereof a resin composition comprising, based on the total amount of the resin components, 50 to 90% by weight of epoxy resins, 5 to 20% by weight of a polyvinyl acetal resin, and 0.1 to 20% by weight of an urethane resin, with the proviso that 0.5 to 40% by weight of the epoxy resins is a rubber-modified epoxy resin; and a multilayer printed wiring board using the resin-coated copper foil therein.
摘要翻译： PCT No.PCT / JP95 / 01335 Sec。 371日期1997年12月31日 102（e）日期1997年12月31日PCT提交1995年7月4日PCT公布。出版物WO97 / 02728 日期1997年1月23日一种用于多层印刷线路板的树脂涂覆铜箔，其特征在于在其一个表面上具有树脂组合物，该树脂组合物基于树脂组分的总量为50至90重量％的环氧树脂树脂，5〜20重量％的聚乙烯醇缩醛树脂和0.1〜20重量％的聚氨酯树脂，条件是0.5〜40重量％的环氧树脂是橡胶改性的环氧树脂; 以及使用其中涂覆有树脂的铜箔的多层印刷线路板。

77. 发明授权

US5661345A Semiconductor device having a single-crystal metal wiring 失效
标题翻译：具有单晶金属布线的半导体器件
公开(公告)号：US5661345A
公开(公告)日：1997-08-26
申请号：US353214
申请日：1994-12-01
申请人： Junichi Wada , Hisashi Kaneko , Kyoichi Suguro , Nobuo Hayasaka , Haruo Okano
发明人： Junichi Wada , Hisashi Kaneko , Kyoichi Suguro , Nobuo Hayasaka , Haruo Okano
IPC分类号： H01L21/3205 , H01L21/285 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/53223 , H01L21/28512 , H01L21/76882 , H01L23/5222 , H01L23/528 , H01L23/53214 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底的表面上形成具有预定图案形状的沟槽; 在与基板的表面反应的同时，在基板上形成金属膜; 并且通过原位退火使金属膜凝聚，其中金属膜在金属膜由于退火而与基板的表面反应之前开始凝聚，同时在金属膜上形成天然氧化物被抑制，通过在预定温度下退火预定时间将金属膜填充到槽中。半导体器件的结构包括绝缘体，其中形成有预定图案形状的沟槽部分和由填充在沟槽部分中的单晶金属制成的电极互连。

78. 发明授权

US5629236A Method of manufacture of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US5629236A
公开(公告)日：1997-05-13
申请号：US506483
申请日：1995-07-25
申请人： Jun-ichi Wada , Hisashi Kaneko , Nobuo Hayasaka
发明人： Jun-ichi Wada , Hisashi Kaneko , Nobuo Hayasaka
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/205
CPC分类号： H01L21/76838 , H01L21/76877 , H01L23/53223 , H01L2924/0002
摘要： The method of manufacturing a semiconductor device, according to the present invention, includes the steps of forming a polycrystal lower-level Al wiring layer on a silicon substrate, forming an interlayer insulation film for covering the lower-level Al wiring layer on the entire surface, forming a connection hole which reaches the lower-level Al wiring layer in the interlayer insulation film, forming a polycrystal upper-level Al wiring layer on a surface of the interlayer insulation film, forming an interlayer insulation film for covering the upper-level Al wiring layer on the entire surface, and forming a single-crystal lower-level Al wiring layer and upper-layer Al wiring layer which are connected to each other in the connection hole by heating the silicon substrate so that the lower-level Al wiring layer and the upper-level Al wiring layer are converted from a polycrystal phase to an amorphous phase, and then cooling the silicon substrate so that the upper-level Al wiring layer is set in a supercooling state.
摘要翻译：根据本发明的制造半导体器件的方法包括在硅衬底上形成多晶低级Al布线层的步骤，形成用于覆盖整个表面上的下层Al布线层的层间绝缘膜在层间绝缘膜中形成到达下层Al布线层的连接孔，在层间绝缘膜的表面上形成多晶上层Al布线层，形成覆盖上层Al的层间绝缘膜布线层，并且通过加热硅基板形成在连接孔中彼此连接的单晶下层Al布线层和上层Al布线层，使得下层Al布线层并且将上层的Al布线层从多晶相转变为非晶相，然后冷却硅基板，使得上层的Al布线层为处于过冷状态。

79. 发明授权

US5409862A Method for making aluminum single crystal interconnections on insulators 失效
标题翻译：在绝缘子上制作铝单晶互连的方法
公开(公告)号：US5409862A
公开(公告)日：1995-04-25
申请号：US035208
申请日：1993-03-22
申请人： Junichi Wada , Hisashi Kaneko , Kyoichi Suguro , Nobuo Hayasaka , Haruo Okano
发明人： Junichi Wada , Hisashi Kaneko , Kyoichi Suguro , Nobuo Hayasaka , Haruo Okano
IPC分类号： H01L21/3205 , H01L21/285 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/44
CPC分类号： H01L23/53223 , H01L21/28512 , H01L21/76882 , H01L23/5222 , H01L23/528 , H01L23/53214 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.
摘要翻译：制造半导体器件的方法包括以下步骤：在衬底的表面上形成具有预定图案形状的沟槽; 在与基板的表面反应的同时，在基板上形成金属膜; 并且通过原位退火使金属膜凝聚，其中金属膜在金属膜由于退火而与基板的表面反应之前开始凝聚，同时在金属膜上形成天然氧化物被抑制，通过在预定温度下退火预定时间将金属膜填充到槽中。半导体器件的结构包括绝缘体，其中形成有预定图案形状的沟槽部分和由填充在沟槽部分中的单晶金属制成的电极互连。

80. 发明授权

US5298112A Method for removing composite attached to material by dry etching 失效
标题翻译：通过干蚀刻除去附着在材料上的复合物的方法
公开(公告)号：US5298112A
公开(公告)日：1994-03-29
申请号：US996864
申请日：1992-12-15
申请人： Nobuo Hayasaka , Tsunetoshi Arikado , Haruo Okano , Keiji Horioka
发明人： Nobuo Hayasaka , Tsunetoshi Arikado , Haruo Okano , Keiji Horioka
IPC分类号： G03F7/42 , H01L21/02 , H01L21/3213 , H01L21/306 , B29C37/00 , B44C1/22 , C23F1/00
CPC分类号： H01L21/02071 , G03F7/427
摘要： A method and apparatus for removing a composite attached to a material to be treated by dry ashing using a gas including a halogen element and a gas including a hydrogen element or using a gas including fluorine, a gas including oxygen and a gas including chlorine in a reaction chamber containing the material therein for use in manufacturing a semiconductor device.
摘要翻译：一种方法和装置，其通过使用包含卤素元素的气体和包含氟元素的气体或使用包含氟的气体，包括氧气和包括氯在内的气体的气体，在干法灰化中附着到待处理材料上反应室含有用于制造半导体器件的材料。

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