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71. 再颁专利

USRE44229E1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：USRE44229E1
公开(公告)日：2013-05-21
申请号：US13365453
申请日：2012-02-03
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，并且内部电压被提供给内部电路。

72. 发明授权

US08426904B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08426904B2
公开(公告)日：2013-04-23
申请号：US13223380
申请日：2011-09-01
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

73. 再颁专利

USRE43222E1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：USRE43222E1
公开(公告)日：2012-03-06
申请号：US12822839
申请日：2010-06-24
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , H03K19/0013
摘要： A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.
摘要翻译：提供了具有降低的消耗电流的半导体集成电路器件。第一降压电路固定地形成低于通过外部端子提供的电源电压的内部电压。根据控制信号，第二降压电路在第一模式和第二模式之间切换。在第一模式中，内部电压由通过外部端子提供的电源电压形成，并通过第二输出端子输出。在第二模式中，形成内部电压的控制系统的工作电流被中断，并且建立了输出高阻抗状态。第一降压电路的第一输出端子和第二降压电路的第二输出端子共同连接，内部电压被提供给内部电路。

74. 发明授权

US07663897B2 Semiconductor circuit device and data processing system 失效
标题翻译：半导体电路设备和数据处理系统
公开(公告)号：US07663897B2
公开(公告)日：2010-02-16
申请号：US12068607
申请日：2008-02-08
申请人： Masashi Horiguchi , Mitsuru Hiraki
发明人： Masashi Horiguchi , Mitsuru Hiraki
IPC分类号： H02M3/06 , G05F1/40
CPC分类号： G05F3/242 , H01L2224/16145 , H01L2224/32245 , H01L2224/48137 , H01L2224/4826 , H01L2224/73215 , Y10T307/76 , H01L2924/00
摘要： Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.
摘要翻译：限制在接通电源时与降压动作相关的电源噪声的发生。降压单元设置有开关电容器型降压电路和串联调节器型降压电路，降压电路的降压电压输出端子共同连接。两个降压电路的降压电压输出端子的共同连接使得两者的并联驱动成为可能的两者的选择性驱动，或者是两者的连续驱动。在连续驱动中，即使在驱动串联调节器型降压电路之后驱动开关电容器型降压电路以向负载提供降压电压，开关电容器型降压电路仅需要由于负载而被补偿放电，并且可以将电容器的充电电流的峰值保持为低。当开关电容器型降压电路的工作开始时，不产生大的冲击电流，并且抑制噪声的发生。

75. 发明申请

US20090010072A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090010072A1
公开(公告)日：2009-01-08
申请号：US12142566
申请日：2008-06-19
申请人： Toshihiro TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro TANAKA , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C11/34
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

76. 发明申请

US20080316192A1 IMAGE DISPLAY DEVICE 失效
标题翻译：图像显示设备
公开(公告)号：US20080316192A1
公开(公告)日：2008-12-25
申请号：US12196659
申请日：2008-08-22
申请人： Hajime AKIMOTO , Mitsuru Hiraki , Hitoshi Nakahara , Takashi Akioka , Yoshiyuki Kaneko , Makoto Tsumura , Yoshiro Mikami
发明人： Hajime AKIMOTO , Mitsuru Hiraki , Hitoshi Nakahara , Takashi Akioka , Yoshiyuki Kaneko , Makoto Tsumura , Yoshiro Mikami
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G06F3/147 , G09G3/20 , G09G3/2007 , G09G3/3648 , G09G3/3677 , G09G5/006 , G09G2300/0814 , G09G2310/027 , G09G2320/10 , G09G2330/021 , G09G2340/02 , G09G2340/0428
摘要： An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.
摘要翻译：图像显示装置具有以矩阵方式布置的多个像素的显示像素区域，用于向像素提供显示信号电压的多个信号线以及用于从要提供的显示信号电压的像素中选择像素的多个像素选择线。像素选择线包括用于选择以矩阵方式布置的像素的行的Y方向选择线和用于选择列的像素的X方向选择线，并且图像显示装置包括其中显示信号电压为从信号线提供给仅同时选择Y方向选择线中的相应一个和X方向选择线中的相应一个的像素中的一个。

77. 发明授权

US07423623B2 Image display device 有权
标题翻译：图像显示装置
公开(公告)号：US07423623B2
公开(公告)日：2008-09-09
申请号：US11062824
申请日：2005-02-23
申请人： Hajime Akimoto , Mitsuru Hiraki , Hitoshi Nakahara , Takashi Akioka , Yoshiyuki Kaneko , Makoto Tsumura , Yoshiro Mikami
发明人： Hajime Akimoto , Mitsuru Hiraki , Hitoshi Nakahara , Takashi Akioka , Yoshiyuki Kaneko , Makoto Tsumura , Yoshiro Mikami
IPC分类号： G09G3/36
CPC分类号： G06F3/147 , G09G3/3648 , G09G2300/0814 , G09G2310/04
摘要： An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.
摘要翻译：图像显示器在由显示像素阵列构成的图像显示部分上显示图像数据。在其中提供用于输入图像数据使得显示像素阵列具有两个具有不同帧速率（> 0）的相邻区域的图像数据输入装置的图像显示器中，或者在由显示像素阵列构成的图像显示部分上显示图像数据提供了图像数据输入装置，其可以以不同的帧速率（> 0）将至少一个运动图像数据和至少一个静止图像数据输入图像显示部分。可以实现几何改变显示像素重写速度的高精度图像显示。运动图像信号输出电路和静止图像信号输出电路将图像数据输出到显示像素阵列，并且它们被提供为彼此独立的电路配置。

78. 发明授权

US07205755B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07205755B2
公开(公告)日：2007-04-17
申请号：US11390276
申请日：2006-03-28
申请人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Tadashi Kameyama
发明人： Takayasu Ito , Mitsuru Hiraki , Masashi Horiguchi , Tadashi Kameyama
IPC分类号： G05F3/16
CPC分类号： G05F3/222
摘要： A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common. A temperature sense voltage is formed from a connecting point of the first and second resistors.
摘要翻译：具有第一电流流经的发射极的第一晶体管的两个发射极电压和至少一个具有发射极的第二晶体管之间的差异，通过该发射极，这样的第二电流达到其电流密度小于第一晶体管流过第一电阻器。第二电阻器设置在第二晶体管的发射极和电路的地电位之间。分别在第一和第二晶体管的集电极之间设置第三电阻器和第四电阻器，以及电源电压。响应于第一晶体管的集电极电压和第二晶体管的集电极电压而形成第一晶体管的集电极电压和第二晶体管的集电极电压相等的这种输出电压，并被提供给第一晶体管的基极和第二个晶体管是共同的。温度感测电压由第一和第二电阻器的连接点形成。

79. 发明申请

US20060132417A1 Semiconductor integrated circuit for liquid crystal display driver 审中-公开
标题翻译：半导体集成电路用于液晶显示驱动
公开(公告)号：US20060132417A1
公开(公告)日：2006-06-22
申请号：US11311161
申请日：2005-12-20
申请人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
发明人： Takeshi Shigenobu , Mitsuru Hiraki , Masashi Horiguchi , Kazuo Okado , Takesada Akiba
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/3674 , G09G3/3685
摘要： In a liquid crystal drive controller formed as a semiconductor integrated circuit having therein a power source circuit including a boosting circuit and driving a source line and a gate line of a TFT liquid crystal panel, the number of external capacitive elements and the number of external terminals for connecting the external capacitive elements are reduced, thereby reducing the size and cost of the chip and an electronic device on which the chip is mounted. As a boosting circuit for generating a voltage for driving a source line of the TFT liquid crystal panel in the liquid crystal controller having therein the power source including the boosting circuit, a boosting circuit having an external capacitive element is used. On the other hand, as a boosting circuit for generating a voltage for driving a gate line, a charge pump having a built-in (on-chip) capacitive element is used.
摘要翻译：在形成为半导体集成电路的液晶驱动控制器中，其中具有包括升压电路并驱动TFT液晶面板的源极线和栅极线的电源电路，外部电容元件的数量和外部端子的数量用于连接外部电容元件的功能减小，从而减小芯片的尺寸和成本以及安装芯片的电子设备。作为用于在其中具有包括升压电路的电源的液晶控制器中产生用于驱动TFT液晶面板的源极线的电压的升压电路，使用具有外部电容元件的升压电路。另一方面，作为用于产生用于驱动栅极线的电压的升压电路，使用具有内置（片上）电容元件的电荷泵。

80. 发明授权

US07057230B2 Nonvolatile semiconductor memory device employing transistors having different gate withstand voltages for enhanced reading speed 有权
标题翻译：采用具有不同栅极耐受电压的晶体管以提高读取速度的非易失性半导体存储器件
公开(公告)号：US07057230B2
公开(公告)日：2006-06-06
申请号：US10484578
申请日：2002-07-22
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

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