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    • 72. 发明授权
    • Air bridge process for forming air gaps
    • 用于形成气隙的气桥过程
    • US06265321B1
    • 2001-07-24
    • US09550264
    • 2000-04-17
    • Simon ChooiMei-Sheng ZhouYi Xu
    • Simon ChooiMei-Sheng ZhouYi Xu
    • H01L2100
    • H01L21/7682H01L21/76807
    • A method for reducing RC delay in integrated circuits by lowering the dielectric constant of the intermetal dielectric material between metal interconnects or metal damascene interconnects is described. The dielectric constant of the intermetal dielectric is lowered by introducing air into the intermetal dielectric between metal interconnections. An air bridge comprising a porous material, preferably amorphous silicon, porous silicon oxide, or porous silsesquioxane, is deposited over a layer containing a reactive organic material. An oxygen plasma treatment or an anisotropic etching through the pores in the air bridge layer removes at least a portion of the reactive material, leaving air plugs within the intermetal dielectric.
    • 描述了通过降低金属互连或金属镶嵌互连之间的金属间电介质材料的介电常数来减小集成电路中的RC延迟的方法。 通过在金属互连之间的金属间电介质中引入空气来降低金属间电介质的介电常数。 包括多孔材料,优选非晶硅,多孔氧化硅或多孔倍半硅氧烷的空气桥被沉积在含有反应性有机材料的层上。 通过空气桥接层中的孔的氧等离子体处理或各向异性蚀刻去除至少一部分反应性材料,从而将空气塞留在金属间电介质内。
    • 75. 发明授权
    • Chemical mechanical polish (CMP) endpoint detection by colorimetry
    • 化学机械抛光(CMP)通过比色法终点检测
    • US6117777A
    • 2000-09-12
    • US902847
    • 1997-07-30
    • Mei-Sheng ZhouSimon Chooi
    • Mei-Sheng ZhouSimon Chooi
    • B24B37/04B24B49/12H01L21/3105H01L21/66H01L21/00
    • B24B37/013B24B37/042B24B49/12H01L21/31053H01L22/26
    • A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a planarizable layer. The planarizable layer has a lower residual portion of the planarizable layer and an upper removable portion of the planarizable layer, where one of the lower residual portion of the planarizable layer and the upper removable portion of the planarizable layer has a colorant incorporated therein. The colorant is positioned at a location which assists in monitoring and controlling an endpoint of a chemical mechanical polish (CMP) planarizing method employed in planarizing the planarizable layer. There is then planarized through the chemical mechanical polish (CMP) planarizing method the planarizable layer while employing the colorant concentration to determine the endpoint of the chemical mechanical polish (CMP) planarizing method.
    • 一种用于制造微电子制造的方法。 首先提供了在微电子制造中使用的衬底。 然后在衬底上形成可平面化的层。 可平面化层具有可平坦化层的较低残余部分和可平面化层的上部可去除部分,其中可平面化层的下部剩余部分和可平面化层的上部可去除部分中的一个具有并入其中的着色剂。 着色剂位于有助于监测和控制用于平坦化可平面化层的化学机械抛光(CMP)平面化方法的端点的位置。 然后通过化学机械抛光(CMP)平面化方法将平坦化层平坦化,同时使用着色剂浓度来确定化学机械抛光(CMP)平面化方法的终点。
    • 76. 发明授权
    • Method to form copper damascene interconnects using a reverse barrier
metal scheme to eliminate copper diffusion
    • 使用反向阻挡金属方案形成铜镶嵌互连以消除铜扩散的方法
    • US6040243A
    • 2000-03-21
    • US398292
    • 1999-09-20
    • Jianxun LiSimon ChooiMei-Sheng Zhou
    • Jianxun LiSimon ChooiMei-Sheng Zhou
    • H01L21/768H01L21/44
    • H01L21/76844H01L21/76805H01L21/76807H01L21/76831
    • A method of fabricating damascene vias has been achieved. Diffusion of copper into dielectric layers due to overetch of the passivation layer is eliminated by a barrier layer. The method can be used to form dual damascene interconnects. Copper traces through an isolation layer are provided overlying a semiconductor substrate. A passivation layer is deposited overlying the copper traces and the isolation layer. A dielectric layer is deposited. A cap layer is deposited. The cap layer and the dielectric layer are patterned to expose the top surface of the passivation layer and to form trenches for the damascene vias. A barrier layer is deposited overlying the passivation layer, the dielectric layer, and the cap layer. The barrier layer is etched though to expose the top surfaces of the cap layer and the passivation layer. The barrier layer isolates the sidewalls of the trenches. The passivation layer is etched through to complete damascene vias. The barrier layer prevents copper sputtering onto the dielectric layer during the step of etching through the passivation layer.
    • 已经实现了制造大马士革过孔的方法。 通过阻挡层消除由于钝化层的过蚀刻而将铜扩散到电介质层中。 该方法可用于形成双镶嵌互连。 通过隔离层的铜迹线设置在半导体衬底上。 沉积在铜迹线和隔离层上的钝化层。 沉积介电层。 沉积盖层。 将盖层和电介质层图案化以暴露钝化层的顶表面并形成用于大马士革过孔的沟槽。 覆盖钝化层,电介质层和覆盖层的阻挡层被沉积。 蚀刻阻挡层以暴露盖层和钝化层的顶表面。 阻挡层隔离沟槽的侧壁。 蚀刻钝化层以完成大马士革过孔。 在蚀刻通过钝化层的步骤期间,阻挡层防止铜溅射到电介质层上。