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71. 发明申请

US20070117317A1 STACKED MEMORY 有权
标题翻译：堆叠内存
公开(公告)号：US20070117317A1
公开(公告)日：2007-05-24
申请号：US11560898
申请日：2006-11-17
申请人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
发明人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C5/025
摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
摘要翻译：在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。堆叠存储器包括存储器核心层，插入器和IF芯片。通过堆叠具有相同布置的存储器核心层，可以处理无视操作和奇偶校验操作两者。此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

72. 发明授权

US07119428B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07119428B2
公开(公告)日：2006-10-10
申请号：US11025634
申请日：2004-12-28
申请人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
发明人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
IPC分类号： H01L23/22 , H01L23/053 , H01L21/44
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
摘要翻译：提供一种能够在其操作期间降低温度升高的半导体器件。在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数的多个半导体元件。

73. 发明申请

US20060145301A1 Semiconductor chip and semiconductor device 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：US20060145301A1
公开(公告)日：2006-07-06
申请号：US11326170
申请日：2006-01-05
申请人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
发明人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
IPC分类号： H01L29/93
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.
摘要翻译：嵌入在半导体衬底中的导线被绝缘膜覆盖，并且偏置电压被施加到半导体衬底或线，以形成从绝缘膜的边缘延伸的耗尽层。或者，在半导体衬底内形成具有与半导体衬底不同的导电类型的半导体层以包围绝缘膜。

74. 发明授权

US06997108B2 Plate-making type printing press, multi-color printing press and plate-making type printing method 失效
公开(公告)号：US06997108B2
公开(公告)日：2006-02-14
申请号：US10222974
申请日：2002-08-19
申请人： Mitsuru Tabuchi , Hitoshi Hirose , Hiroya Nishii , Hajime Yagi , Masahiro Matsubara , Hiroaki Ikeda , Toshihiko Yamanaka
发明人： Mitsuru Tabuchi , Hitoshi Hirose , Hiroya Nishii , Hajime Yagi , Masahiro Matsubara , Hiroaki Ikeda , Toshihiko Yamanaka
IPC分类号： B41F7/02 , B41M5/00
CPC分类号： B41C1/1075
摘要： The plate-making printing press is constructed by installing a plate-making apparatus in a printing press that supplies ink and dampening water to a printing plate and performs printing on a medium. In order to realize a high-precision plate-making operation, the printing press is equipped with a target disposed on the printing cylinder and a sensor for detecting the target and provided on the writing device, and the zero point of the encoder is corrected. Furthermore, at the time of plate-making, the adjustment mechanism is operated so that the printing cylinder is returned to the position of the point of origin.

75. 发明申请

US20050213819A1 Form recognition system, method, program, and storage medium 失效
标题翻译：表单识别系统，方法，程序和存储介质
公开(公告)号：US20050213819A1
公开(公告)日：2005-09-29
申请号：US11086031
申请日：2005-03-22
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G06F19/00 , G06K9/20 , G06K9/46 , G06Q10/10
CPC分类号： G06K9/00449
摘要： The similarity between a search form and a registered form is calculated on a page-by-page basis in a predetermined order. Every time the page similarity is calculated, it is determined whether or not a value representing the similarity is smaller than a predetermined threshold value. If it is determined that the similarity value is smaller than the threshold value, the registered form is removed, at this point, from candidates for a recognition target. A form having a possibility of page repetition can also be recognized.
摘要翻译：以预定的顺序逐页地计算搜索表单和注册表单之间的相似性。每次计算页面相似度时，确定表示相似度的值是否小于预定阈值。如果确定相似度值小于阈值，则在此处从注册表的候选者中移除注册形式。也可以识别具有页重复的可能性的形式。

76. 发明授权

US06943921B2 Digital image forming apparatus 有权
标题翻译：数字图像形成装置
公开(公告)号：US06943921B2
公开(公告)日：2005-09-13
申请号：US09739659
申请日：2000-12-20
申请人： Hironobu Nakata , Hiroaki Ikeda , Kaoru Tada , Tomoyuki Atsumi , Hiroyasu Ito
发明人： Hironobu Nakata , Hiroaki Ikeda , Kaoru Tada , Tomoyuki Atsumi , Hiroyasu Ito
IPC分类号： B41J21/00 , G03G15/36 , H04N1/00
CPC分类号： H04N1/00405 , H04N1/00411 , H04N1/00413 , H04N1/0049 , H04N1/00567 , H04N1/00639
摘要： A digital image forming apparatus arranges an image of a specified image document among a plurality of documents on a spread page located on the innermost side of saddle stitch type prints in gathering in easy operation with high reliability. A digital image forming apparatus is equipped with: an image reader for reading images of a plurality of pages of documents and outputting an image data of each image; a printer for forming images on both sides of a paper sheet based on inputted image data; array setting means for setting allotment of each of paper sheets for the documents read by the image reader so that prints for saddle stitching are obtained by using the printer and that an image of a specified document among the documents is arranged on a spread page of the saddle stitch type prints; and control means for inputting the image data outputted by the image reader to the printer in an order changed based on the array setting set by the array setting means.
摘要翻译：数字图像形成装置以高可靠性收集易于操作的方式，将位于位于骑马钉式打印机的最内侧的扩展页面上的多个文档中的指定图像文档的图像进行排列。数字图像形成装置配备有：图像读取器，用于读取多页文档的图像并输出每个图像的图像数据; 一种用于基于输入的图像数据在纸张的两面上形成图像的打印机; 用于设置由图像读取器读取的文档的每张纸张的分配的阵列设置装置，使得通过使用打印机获得骑马装订的打印，并且将文档中的指定文档的图像布置在马鞍式印花; 以及控制装置，用于根据由阵列设置装置设置的阵列设置改变图像读取器输出的图像数据到打印机。

77. 发明申请

US20050158663A1 Regenerative plate making and printing process, and plate making and printing apparatus 审中-公开
公开(公告)号：US20050158663A1
公开(公告)日：2005-07-21
申请号：US11047690
申请日：2005-02-02
申请人： Mitsuru Tabuchi , Masahiro Matsubara , Hiroaki Ikeda , Toshiyuki Urano , Takuya Uematsu , Yuji Mizuho
发明人： Mitsuru Tabuchi , Masahiro Matsubara , Hiroaki Ikeda , Toshiyuki Urano , Takuya Uematsu , Yuji Mizuho
IPC分类号： B41C1/10 , B41F7/02 , B41N1/08 , B41N3/00 , B41N3/03 , B41N3/06 , G03F7/16 , G03F7/18 , G03F7/24 , G03F7/30 , G03F7/42 , G03C1/492
CPC分类号： B41N3/006 , B41C1/1008 , B41C2210/02 , B41C2210/04 , B41C2210/08 , B41C2210/22 , B41C2210/24 , B41C2210/262 , B41F7/02 , B41N1/083 , B41N3/036 , B41N3/06 , B41P2227/70 , G03F7/16 , G03F7/18 , G03F7/24 , G03F7/3035 , G03F7/422 , G03F7/425
摘要： The regenerative plate making and printing process, and plate making and printing apparatus of the present invention are applied to a printing system requiring a separate developing step independent of a printing step. In accordance with the present invention, by repeatedly conducting (A) a photosensitive layer-coating step of coating a photosensitive plate material onto a substrate to prepare a photosensitive lithographic plate having a photosensitive layer thereon; (B) an exposure step of exposing the photosensitive layer to image light; (C) a development step of supplying a plate-treating agent to the photosensitive layer to form developed images thereon; (D) a printing step of supplying a printing ink and dampening water to surfaces of the thus obtained images to conduct printing; and (E) a substrate regeneration step of removing the image portions from the substrate to regenerate the substrate, on the same rotary drum or conveyer, it is possible to considerably improve the working efficiency and stably provide high-quality images.

78. 发明授权

US06882241B2 Method, memory system and memory module board for avoiding local incoordination of impedance around memory chips on the memory system 有权
标题翻译：方法，存储器系统和存储器模块板，用于避免存储器系统上的存储器芯片周围的阻抗的局部不协调
公开(公告)号：US06882241B2
公开(公告)日：2005-04-19
申请号：US10255987
申请日：2002-09-26
申请人： Hisashi Abo , Hiroaki Ikeda
发明人： Hisashi Abo , Hiroaki Ikeda
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G11C5/00 , G11C5/06 , H01L27/10 , H05K1/02 , H05K1/14 , H03H7/38 , H03H5/00
CPC分类号： H05K1/14 , G11C5/063 , H01L2924/0002 , H05K1/0237 , H01L2924/00
摘要： A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.
摘要翻译：数据总线的信号线包括第一板上的第一布线和第二板上的第二布线。第二板安装在第一板上，以串联连接第一和第二导线以建立信号线。半导体器件与第二线连接。在这种数据总线系统中，根据第二板上的半导体器件的附加电容来确定第二布线的阻抗，以便使第一板的阻抗与第二板的阻抗相协调。

79. 发明授权

US06862246B2 Semiconductor apparatus which prevents generating noise and being influenced by noise 有权
标题翻译：防止产生噪声并受噪声影响的半导体装置
公开(公告)号：US06862246B2
公开(公告)日：2005-03-01
申请号：US10454404
申请日：2003-06-04
申请人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
发明人： Seiji Funaba , Yoji Nishio , Hiroaki Ikeda
IPC分类号： G06F1/12 , G11C7/10 , G11C7/22 , G11C11/407 , H01L21/822 , H01L27/04 , H03K3/03 , H03K5/00 , H03L7/00 , H03L7/089 , H03L7/091 , H03L7/099 , G11C8/00
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , H03K3/0322 , H03K2005/00078 , H03K2005/00208 , H03L7/0895 , H03L7/091 , H03L7/0995
摘要： The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.
摘要翻译：本发明提供一种包括内部时钟生成单元和数据存储单元的半导体装置。内部时钟发生单元基于外部时钟信号和时钟控制信号产生内部时钟信号。数据存储单元，其基于内部时钟信号进行数据处理。内部时钟发生单元执行同步控制，使得内部时钟信号与外部时钟信号同步。数据存储单元基于数据处理生成时钟控制信号，并将时钟控制信号输出到内部时钟发生单元，以控制同步控制。数据存储单元可以控制内部时钟生成单元，使得在数据处理是数据读取处理的同时控制暂时中止或暂时抑制。

80. 发明授权

US06522590B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06522590B2
公开(公告)日：2003-02-18
申请号：US09783109
申请日：2001-02-14
申请人： Yoshinori Matsui , Hiroaki Ikeda
发明人： Yoshinori Matsui , Hiroaki Ikeda
IPC分类号： G11C700
CPC分类号： G11C29/44
摘要： A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.
摘要翻译：一种半导体存储器件，其使用共享一个数据传输总线的冗余存储器单元簇来执行多个缺陷的缺陷恢复，并提供改进的恢复速率。半导体存储器件由主存储器，作为高速缓存存储器起作用的子存储器和多个数据传输总线线路构成，数据传输总线被配置为使得数据可以在所述主存储器和所述子存储器之间双向传输 ; 并且基于用于所述副存储器的地址信号（子存储器列选择信号SYm）和所述主存储器中的地址信号（主存储器行选择信号DXn和存储体选择信号BS）对位于所述主存储器中的缺陷进行缺陷恢复，其对应于所述地址。

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