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71. 发明申请

US20060267208A1 Method of forming closed air gap interconnects and structures formed thereby 失效
标题翻译：形成闭合气隙互连件和由此形成的结构的方法
公开(公告)号：US20060267208A1
公开(公告)日：2006-11-30
申请号：US11405283
申请日：2006-04-17
申请人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
发明人： Matthew Colburn , Timothy Dalton , Elbert Huang , Simon Karecki , Satya Nitta , Sampath Purushothaman , Katherine Saenger , Maheswaran Surendra
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76807 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.
摘要翻译：描述了形成闭合气隙互连结构的方法。在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板孔阵列然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。描述该方法的几个实施例和所得到的结构。

72. 发明申请

US20060183308A1 Method of etching dual pre-doped polysilicon gate stacks using carbon-containing gases additions 失效
标题翻译：使用含碳气体添加剂蚀刻双预掺杂多晶硅栅极叠层的方法
公开(公告)号：US20060183308A1
公开(公告)日：2006-08-17
申请号：US10730891
申请日：2003-12-10
申请人： Ying Zhang , Timothy Dalton , Wesley Natzle
发明人： Ying Zhang , Timothy Dalton , Wesley Natzle
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L21/28123 , H01L21/32137 , H01L21/32139
摘要： A method for making dual pre-doped gate stacks used in semiconductor applications such as complementary metal oxide semiconductor (CMOS) devices and metal oxide semiconductor field effect transistors (MOSFETs) is provided. The method involves providing at least one pre-doped conductive layer, such as poly silicon (poly-Si), on a gate stack and etching by exposing the conductive layer to an etching composition comprising at least one carbon containing gas. The carbon containing gas can be selected from gases having the general formula CxHy, such as, for example, CH4, C2H2, C2H4, and C2H6. The carbon containing gas can further be selected from gases having the general formula CxHyA, wherein a can represent one or more additional substituents selected from O, N, P, S, F, Cl, Br, and I. The processes can result in dual pre-doped gate stacks having essentially vertical sidewalls and further having a width of at least about 3 nm, such as from about 5 nm to about 150 nm.
摘要翻译：提供了在半导体应用中使用诸如互补金属氧化物半导体（CMOS）器件和金属氧化物半导体场效应晶体管（MOSFET）的双预预掺杂栅叠层的方法。该方法包括在栅叠层上提供至少一个预先掺杂的导电层，例如多晶硅（poly-Si），以及通过将导电层暴露于含有至少一种含碳气体的蚀刻组合物进行蚀刻。含碳气体可以选自具有通式C x H H y H的气体，例如CH 4，C 3， H 2 H 2，C 2 H 4，和C 2 H 2， 6 。含碳气体还可以选自具有通式C x H A A A的气体，其中a可以表示一个或多个选自O，N，P ，S，F，Cl，Br和I.该工艺可以导致具有基本上垂直的侧壁并且还具有至少约3nm，例如约5nm至约150nm的宽度的双预掺杂栅叠层。

73. 发明授权

US08471306B2 Double-sided integrated circuit chips 失效
标题翻译：双面集成电路芯片
公开(公告)号：US08471306B2
公开(公告)日：2013-06-25
申请号：US13192608
申请日：2011-07-28
申请人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Jeffrey Peter Gambino , Mark David Jaffe , Paul David Kartschoke , Stephen Ellinwood Luce , Anthony Kendall Stamper
IPC分类号： H01L29/80 , H01L29/04 , H01L31/036
CPC分类号： G06F17/5077 , H01L21/6835 , H01L21/76895 , H01L21/84 , H01L23/481 , H01L23/535 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L29/045 , H01L2221/6835 , H01L2221/68359 , H01L2221/68368 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2924/01019 , H01L2924/01029 , H01L2924/0132 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/01007 , H01L2924/01022 , H01L2924/00
摘要： A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.
摘要翻译：双面集成电路芯片，制造双面集成电路芯片的方法和双面集成电路芯片的设计结构。该方法包括从具有在其中制造的器件的两个绝缘体上硅晶片上去除背面硅，并利用掩埋氧化物层将它们背对背地接合。然后在上晶片中形成与下晶片中的器件接触，并在上晶片上形成布线层。下晶片可以包括布线水平。下部晶片可以包括用于触点的着陆焊盘。与下晶片的硅层的接触可以被硅化。

74. 发明授权

US07863734B2 Dual-sided chip attached modules 有权
标题翻译：双面芯片连接模块
公开(公告)号：US07863734B2
公开(公告)日：2011-01-04
申请号：US12186655
申请日：2008-08-06
申请人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
发明人： Kerry Bernstein , Timothy Dalton , Timothy Harrison Daubenspeck , Jeffrey Peter Gambino , Mark David Jaffe , Christopher David Muzzy , Wolfgang Sauter , Edmund Sprogis , Anthony Kendall Stamper
IPC分类号： H01L23/34 , H01L23/48
CPC分类号： H01L24/10 , H01L23/13 , H01L23/481 , H01L23/49833 , H01L23/5385 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L2224/13 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/15787 , H05K1/145 , H05K3/222 , H05K2201/10674 , Y10T436/171538 , Y10T436/172307 , H01L2924/00014 , H01L2924/00
摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.
摘要翻译：一种电子装置和包装电子装置的方法。该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

75. 发明申请

US20080093342A1 ETCHING APPARATUS FOR SEMICONDUTOR FABRICATION 审中-公开
标题翻译：用于半导体制造的蚀刻装置
公开(公告)号：US20080093342A1
公开(公告)日：2008-04-24
申请号：US11962271
申请日：2007-12-21
申请人： Timothy Dalton , Emily Gallagher , Louis Kindt , Carey Thiel , Andrew Watts
发明人： Timothy Dalton , Emily Gallagher , Louis Kindt , Carey Thiel , Andrew Watts
IPC分类号： C23F1/00
CPC分类号： H01J37/32706 , H01J37/32091 , H01J37/32541
摘要： Method of operating an apparatus which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method is as follows. A substrate to be etched is placed between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments. N bias powers are determined which when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas. Then, the bias power system is used to apply the N bias powers the N cathode segments.
摘要翻译：操作能够以基本上相同的蚀刻速率蚀刻具有不同图案密度的衬底的不同衬底蚀刻区域的装置的方法。该装置包括（a）室; （b）室中的阳极和阴极; 和（c）耦合到所述阴极的偏置功率系统，其中所述阴极包括多个阴极段。操作方法如下。要蚀刻的衬底放置在阳极和阴极之间，其中衬底包括N个衬底蚀刻区域，并且N个衬底蚀刻区域直接在N个阴极段上方。确定N偏置功率，当在衬底的蚀刻期间施加到N个阴极段时，将产生对于N个衬底蚀刻区域基本上相同的蚀刻速率。然后，使用偏置功率系统对N个阴极段施加N个偏置功率。

76. 发明申请

US20080047118A1 VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF 审中-公开
标题翻译：使用间隔型电极的垂直平行平板电容器及其制造方法
公开(公告)号：US20080047118A1
公开(公告)日：2008-02-28
申请号：US11924807
申请日：2007-10-26
申请人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
发明人： Timothy Dalton , Jeffrey Gambino , Anthony Stamper
IPC分类号： H01G7/00
CPC分类号： H01G4/33 , H01G4/236 , H01L28/91 , Y10T29/435
摘要： A capacitor structure uses an aperture located within a dielectric layer in turn located over a substrate. A pair of conductor interconnection layers embedded within the dielectric layer terminates at a pair of opposite sidewalls of the aperture. A pair of capacitor plates is located upon the pair of opposite sidewalls of the aperture and contacting the pair of conductor interconnection layers, but not filling the aperture. A capacitor dielectric layer is located interposed between the pair of capacitor plates and filling the aperture. The pair of capacitor plates may be formed using an anisotropic unmasked etch followed by a masked trim etch. Alternatively, the pair of capacitor plates may be formed using an unmasked anisotropic etch only, when the pair of opposite sidewalls of the aperture is vertical and separated by a second pair of opposite sidewalls that is outward sloped.
摘要翻译：电容器结构使用位于电介质层内的开口依次位于衬底上。嵌入电介质层内的一对导体互连层终止于孔的一对相对的侧壁。一对电容器板位于孔的一对相对的侧壁上，并接触一对导体互连层，但不填充孔。电容器介质层位于一对电容器板之间并填充孔。可以使用各向异性无掩模蚀刻，然后进行掩模修整蚀刻来形成该对电容器板。或者，一对电容器板可以仅使用未屏蔽的各向异性蚀刻形成，当孔的一对相对的侧壁是垂直的并且被向外倾斜的第二对相对的侧壁隔开时。

77. 发明申请

US20070266129A1 THREE-DIMENSIONAL NETWORKING STRUCTURE 有权
标题翻译：三维网络结构
公开(公告)号：US20070266129A1
公开(公告)日：2007-11-15
申请号：US11382967
申请日：2006-05-12
申请人： Kerry Bernstein , Timothy Dalton , Marc Faucher , Peter Sandon
发明人： Kerry Bernstein , Timothy Dalton , Marc Faucher , Peter Sandon
IPC分类号： G06F15/173 , H01L23/02
CPC分类号： H01L25/0652 , H01L25/18 , H01L2225/06562 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a multi-layer silicon stack architecture including: one or more processing layers including one or more computing elements; one or more networking layers disposed between the processing layers, the network layer includes one or more networking elements, wherein each computing element includes a plurality of network connections to adjacently disposed networking elements.
摘要翻译：本文公开了一种多层硅堆叠架构，其包括：一个或多个处理层，包括一个或多个计算元件; 布置在处理层之间的一个或多个网络层，网络层包括一个或多个网络元件，其中每个计算元件包括到相邻布置的网络元件的多个网络连接。

78. 发明申请

US20070161226A1 Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity 失效
标题翻译：双镶嵌工艺流程可实现极少的ULK膜修饰和增强的堆叠完整性
公开(公告)号：US20070161226A1
公开(公告)日：2007-07-12
申请号：US11328981
申请日：2006-01-10
申请人： Timothy Dalton , Nicholas Fuller , Satyanarayana Nitta
发明人： Timothy Dalton , Nicholas Fuller , Satyanarayana Nitta
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76808 , H01L21/76829
摘要： Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.
摘要翻译：本文提供了具有最小化学计量变化的有机硅酸盐玻璃层间介电材料和任选的用于半导体器件的完整有机粘合促进剂的互连结构。互连结构能够提供改进的器件性能，功能性和可靠性，因为与常规使用的那些相比，堆叠的有效介电常数降低，因为使用沉积在电介质上的牺牲聚合物材料和任选的有机粘合促进剂在灰化图案材料之前完成的阻挡层开口步骤。该牺牲膜在后续的灰化步骤期间保护电介质和任选的有机粘合促进剂免于修饰/消耗，在此期间除去聚合物膜。

79. 发明申请

US20070132067A1 WAFER-TO-WAFER ALIGNMENTS 失效
标题翻译： WAFER-WAFER对准
公开(公告)号：US20070132067A1
公开(公告)日：2007-06-14
申请号：US11557668
申请日：2006-11-08
申请人： Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Stephen Luce , Edmund Sprogis
发明人： Timothy Dalton , Jeffrey Gambino , Mark Jaffe , Stephen Luce , Edmund Sprogis
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54453 , H01L2225/06513 , H01L2225/06531 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.
摘要翻译：用于对准晶片的结构及其操作方法。该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。第一和第二半导体晶片经由公共表面彼此直接物理接触。如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则包括第一电容耦合结构和第二电容耦合结构的第一电容器的电容中的至少10 -18 F。第一个方向基本上平行于共同的表面。

80. 发明授权

US07125792B2 Dual damascene structure and method 有权
标题翻译：双镶嵌结构和方法
公开(公告)号：US07125792B2
公开(公告)日：2006-10-24
申请号：US10685055
申请日：2003-10-14
申请人： Kaushik Kumar , Douglas C. La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
发明人： Kaushik Kumar , Douglas C. La Tulipe , Timothy Dalton , Larry Clevenger , Andy Cowley , Erdem Kaltalioglu , Jochen Schacht
IPC分类号： H01L21/4763
CPC分类号： H01L21/76835 , H01J37/32862 , H01L21/02046 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136 , H01L21/76811
摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.
摘要翻译：一种双镶嵌结构及其制造方法。绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案不同于第一图案。第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。

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