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71. 发明授权

US08281075B2 Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效
标题翻译：使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法
公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F13/00 , G06F13/36 , G06F13/38 , G06F9/315
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译：用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中）记忆）。从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。可信内核可能包含在管理程序或操作系统中。

72. 发明授权

US07849298B2 Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效
标题翻译：通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制
公开(公告)号：US07849298B2
公开(公告)日：2010-12-07
申请号：US12352462
申请日：2009-01-12
申请人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
摘要翻译：公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。软状态经由存储器接口传送到与处理器相关联的存储器。优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。此后，当再次执行处理时，可以从存储器恢复存储的软状态。

73. 发明申请

US20100268890A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权
标题翻译：信息处理系统，具有立即调度在双存储单元缓存中的负载运算，具有单个分配到写/读数据流
公开(公告)号：US20100268890A1
公开(公告)日：2010-10-21
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

74. 发明申请

US20100268883A1 Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory 有权
标题翻译：信息处理系统，即时调度负载操作和细粒度访问高速缓存
公开(公告)号：US20100268883A1
公开(公告)日：2010-10-21
申请号：US12424332
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。控制逻辑确定每个加载操作或存储操作的大小要求。当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。

75. 发明授权

US07689777B2 Cache member protection with partial make MRU allocation 失效
标题翻译：缓存成员保护部分使MRU分配
公开(公告)号：US07689777B2
公开(公告)日：2010-03-30
申请号：US11951770
申请日：2007-12-06
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下，否定受保护成员的选择。

76. 发明申请

US20090198867A1 METHOD FOR CHAINING MULTIPLE SMALLER STORE QUEUE ENTRIES FOR MORE EFFICIENT STORE QUEUE USAGE 有权
标题翻译：用于链接更多有效存储队列使用的多个小型存储队列的方法
公开(公告)号：US20090198867A1
公开(公告)日：2009-08-06
申请号：US12023600
申请日：2008-01-31
申请人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
发明人： Guy Lynn Guthrie , Thomas Leo Jeremiah , William Lloyd McNeil , Hugh Shen , William John Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0815
摘要： A computer implemented method, a processor chip, a data processing system, and computer program product in a data processing system process information in a store cache of a data processing system. The store cache receives a first entry that includes a first address indicating a first segment of a cache line. The store cache then receives a second entry including a second address indicating a second segment of the cache line. Responsive to the first segment not being equal to the second segment, the first entry is chained to the second entry.
摘要翻译：数据处理系统中的计算机实现方法，处理器芯片，数据处理系统和计算机程序产品，处理数据处理系统的存储高速缓存中的信息。存储高速缓存接收包括指示高速缓存行的第一段的第一地址的第一条目。存储高速缓存然后接收包括指示高速缓存行的第二段的第二地址的第二条目。响应于第一段不等于第二段，第一个条目链接到第二个条目。

77. 发明申请

US20090150617A1 CACHE MECHANISM AND METHOD FOR AVOIDING CAST OUT ON BAD VICTIM SELECT AND RECYCLING VICTIM SELECT OPERATION 有权
标题翻译：高速缓存机制和方法，用于避免在BAD VICTIM SELECT和RECYCLING VICTIM选择操作
公开(公告)号：US20090150617A1
公开(公告)日：2009-06-11
申请号：US11951783
申请日：2007-12-06
申请人： ROBERT H. BELL, JR. , Guy Lynn Guthrie , William John Starke
发明人： ROBERT H. BELL, JR. , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译：一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。

78. 发明授权

US07490202B2 Data processing system and method for efficient L3 cache directory management 有权
公开(公告)号：US07490202B2
公开(公告)日：2009-02-10
申请号：US11956112
申请日：2007-12-13
申请人： Guy Lynn Guthrie , William John Starke , Derek Edward Williams , Philip G. Williams
发明人： Guy Lynn Guthrie , William John Starke , Derek Edward Williams , Philip G. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

79. 发明申请

US20080177953A1 CACHE MEMBER PROTECTION WITH PARTIAL MAKE MRU ALLOCATION 失效
标题翻译：缓存成员保护，部分成为MRU分配
公开(公告)号：US20080177953A1
公开(公告)日：2008-07-24
申请号：US11951770
申请日：2007-12-06
申请人： ROBERT H. BELL , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： ROBERT H. BELL , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译：一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。保护位用作用于标识要保护的同余类的成员的位置的指针。在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。

80. 发明授权

US07401189B2 Pipelining D states for MRU steerage during MRU/LRU member allocation 失效
标题翻译：在MRU / LRU成员分配过程中，管理MRU操纵的D状态
公开(公告)号：US07401189B2
公开(公告)日：2008-07-15
申请号：US11054067
申请日：2005-02-09
申请人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert H. Bell, Jr. , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译：用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。信息被锁存，然后传递给MRU向量生成逻辑。生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。

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