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1. 发明申请

US20100268890A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权
标题翻译：信息处理系统，具有立即调度在双存储单元缓存中的负载运算，具有单个分配到写/读数据流
公开(公告)号：US20100268890A1
公开(公告)日：2010-10-21
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

2. 发明申请

US20100268887A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH DUAL DISPATCH INTO WRITE/READ DATA FLOW 有权
标题翻译：信息处理系统具有立即调度双币种缓存中的负载操作，双重分配到写/读数据流
公开(公告)号：US20100268887A1
公开(公告)日：2010-10-21
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

3. 发明申请

US20100268895A1 INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS 审中-公开
标题翻译：信息处理系统，立即加载运行
公开(公告)号：US20100268895A1
公开(公告)日：2010-10-21
申请号：US12424284
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/126
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。

4. 发明申请

US20100268883A1 Information Handling System with Immediate Scheduling of Load Operations and Fine-Grained Access to Cache Memory 有权
标题翻译：信息处理系统，即时调度负载操作和细粒度访问高速缓存
公开(公告)号：US20100268883A1
公开(公告)日：2010-10-21
申请号：US12424332
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0822
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption. The control logic determines the size requirement of each load operation or store operation. When the cache memory system performs a store operation or load operation, the memory system accesses the portion of a cache line it needs to perform the operation instead of accessing an entire cache line.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。控制逻辑确定每个加载操作或存储操作的大小要求。当高速缓冲存储器系统执行存储操作或加载操作时，存储器系统访问它需要执行操作的高速缓存行的部分，而不是访问整个高速缓存行。

5. 发明授权

US10489293B2 Information handling system with immediate scheduling of load operations 有权
公开(公告)号：US10489293B2
公开(公告)日：2019-11-26
申请号：US12424284
申请日：2009-04-15
申请人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
发明人： Sanjeev Ghai , Guy Lynn Guthrie , Stephen Powell , William John Starke
IPC分类号： G06F12/08 , G06F12/0855 , G06F12/126
CPC分类号： G06F12/0855 , G06F12/126
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

6. 发明申请

US20100262735A1 TECHNIQUES FOR TRIGGERING A BLOCK MOVE USING A SYSTEM BUS WRITE COMMAND INITIATED BY USER CODE 失效
标题翻译：使用用户代码启动的系统总线写命令来触发块移动的技术
公开(公告)号：US20100262735A1
公开(公告)日：2010-10-14
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F13/14 , G06F12/00 , G06F12/08
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command (via the system bus) process the specific request-type command when the core permission controls are the same as the respective slave permission controls.
摘要翻译：用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中）记忆）。从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令（通过系统总线）的从设备处理特定请求类型命令。

7. 发明授权

US07284102B2 System and method of re-ordering store operations within a processor 失效
标题翻译：在处理器内重新排序存储操作的系统和方法
公开(公告)号：US07284102B2
公开(公告)日：2007-10-16
申请号：US11054450
申请日：2005-02-09
申请人： Guy Lynn Guthrie , Hugh Shen , William John Starke , Derek Edward Williams
发明人： Guy Lynn Guthrie , Hugh Shen , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/3824 , G06F12/0817
摘要： A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.
摘要翻译：一种用于重新排序从处理器核到存储队列的存储操作的系统和方法。当存储队列从处理器核心接收到新的处理器发出的存储操作时，存储队列控制器在存储队列中分配新的条目。响应于在商店队列中分配新条目，商店队列控制器确定新条目是否依赖于商店队列中的至少一个其他有效条目。响应于确定新条目取决于存储队列中的至少一个其他有效条目，存储队列控制器禁止向RC调度逻辑请求新条目，直到新条目依赖于其上的每个有效条目已经成功通过RC调度逻辑调度到RC机器。

8. 发明授权

US08140765B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow 有权
标题翻译：信息处理系统，可以在双行缓存中立即调度负载操作，并单次调度到写入/读取数据流
公开(公告)号：US08140765B2
公开(公告)日：2012-03-20
申请号：US12424228
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/28
CPC分类号： G06F12/0846 , G06F12/0897
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

9. 发明授权

US08195880B2 Information handling system with immediate scheduling of load operations in a dual-bank cache with dual dispatch into write/read data flow 有权
标题翻译：信息处理系统，具有双重缓存中的负载操作的即时调度，具有双重调度到写入/读取数据流
公开(公告)号：US08195880B2
公开(公告)日：2012-06-05
申请号：US12424255
申请日：2009-04-15
申请人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
发明人： Sanjeev Gai , Guy Lynn Guthrie , Hugh Shen , William John Starke
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0811
摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides dual dispatch points into the data flow to the dual cache banks of the L2 cache memory.
摘要翻译：信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。缓存系统向数据流提供双调度点到二级高速缓冲存储器的双缓存组。

10. 发明授权

US08281075B2 Processor system and methods of triggering a block move using a system bus write command initiated by user code 失效
标题翻译：使用由用户代码启动的系统总线写入命令来触发块移动的处理器系统和方法
公开(公告)号：US08281075B2
公开(公告)日：2012-10-02
申请号：US12423355
申请日：2009-04-14
申请人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
发明人： Lakshminarayana Baba Arimilli , Brian Mitchell Bass , David Wayne Cummings , Bernard Charles Drerup , Guy Lynn Guthrie , Ronald Nick Kalla , Hugh Shen , Michael Steven Siegel , William John Starke , Derek Edward Williams
IPC分类号： G06F13/00 , G06F13/36 , G06F13/38 , G06F9/315
CPC分类号： G06F12/1458 , G06F9/30047 , G06F9/30087 , G06F12/0893
摘要： A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.
摘要翻译：用户代码触发系统总线写命令的技术包括识别用户指令序列中的特定存储型指令。特定存储型指令被转换成特定的请求类型命令，其被配置为包括核心权限控制（存储在可信内核中的处理器核心的核心配置寄存器中）和用户创建的数据（存储在高速缓存中）记忆）。从设备通过具有相应从属权限控制的寄存器空间（可由可信内核访问）进行配置。然后，经由系统总线从高速缓冲存储器发送特定的请求类型命令。在这种情况下，当核心权限控制与相应从属许可控制相同时，接收特定请求类型命令的从设备处理特定请求类型命令。可信内核可能包含在管理程序或操作系统中。

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