专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20080171432A1 Circuit Structure with Low Dielectric Constant Regions and Method of Forming Same 有权
标题翻译：具有低介电常数区域的电路结构及其形成方法
公开(公告)号：US20080171432A1
公开(公告)日：2008-07-17
申请号：US11623478
申请日：2007-01-16
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Louis C. Hsu , Wai-Kin Li
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682
摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of inter connect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.
摘要翻译：一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。具有多个互连开口和多个间隙开口的第一电介质层形成在第一布线层的上方。互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

72. 发明申请

US20070275552A1 STRUCTURE FOR REDUCING LATERAL FRINGE CAPACITANCE IN SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME 失效
标题翻译：用于减少半导体器件中的侧向电容的结构及其形成方法
公开(公告)号：US20070275552A1
公开(公告)日：2007-11-29
申请号：US11420253
申请日：2006-05-25
申请人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
发明人： Lawrence A. Clevenger , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca , Vidhya Ramachandran , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.
摘要翻译：半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第导线。

73. 发明授权

US07187085B2 Semiconductor device including dual damascene interconnections 有权
标题翻译：半导体器件包括双镶嵌互连
公开(公告)号：US07187085B2
公开(公告)日：2007-03-06
申请号：US10853492
申请日：2004-05-26
申请人： Lawrence A. Clevenger , Larry A. Nesbit
发明人： Lawrence A. Clevenger , Larry A. Nesbit
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76877 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.
摘要翻译：在半导体衬底上形成互连的方法（和结构）包括在形成在半导体衬底上的电介质中形成相对窄的第一结构，在形成在半导体衬底上的电介质中形成相对较宽的第二结构，所述第一和第二结构使得所述第一结构基本上被填充并且所述第二结构基本上未被填充，并且在所述衬套上形成金属化以完全填充所述第二结构。

74. 发明授权

US06964892B2 N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same 失效
标题翻译： N沟道金属氧化物半导体（NMOS）驱动电路及其制造方法
公开(公告)号：US06964892B2
公开(公告)日：2005-11-15
申请号：US10155731
申请日：2002-05-28
申请人： Lawrence A. Clevenger , Rama Divakaruni , Louis Lu-Chen Hsu , Yujun Li
发明人： Lawrence A. Clevenger , Rama Divakaruni , Louis Lu-Chen Hsu , Yujun Li
IPC分类号： H01L23/522 , H01L21/225 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/8238 , H01L21/00 , H01L21/84
CPC分类号： H01L29/6659 , H01L21/2251 , H01L21/76895 , H01L27/088 , Y10S438/969
摘要： An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack.
摘要翻译： N沟道金属氧化物半导体（NMOS）驱动电路（及其制造方法）包括形成在衬底上并具有通过低浓度注入形成的源极和漏极的升压栅极堆叠以及耦合到升压栅极堆叠。

75. 发明授权

US06720602B2 Dynamic random access memory (DRAM) cell with folded bitline vertical transistor and method of producing the same 有权
标题翻译：具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US06720602B2
公开(公告)日：2004-04-13
申请号：US10101992
申请日：2002-03-21
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl D. Radens
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl D. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译：半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的一对间隔字线导线。

76. 发明授权

US06638681B2 X-ray printing personalization technique 失效
标题翻译： X射线印刷个性化技术
公开(公告)号：US06638681B2
公开(公告)日：2003-10-28
申请号：US10281677
申请日：2002-10-28
申请人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
发明人： Lawrence A. Clevenger , David B. Goland , Louis L. Hsu , Joseph F. Shepard, Jr. , Subhash L. Shinde
IPC分类号： G03F700
CPC分类号： H05K3/02 , B32B2310/085 , B32B2311/04 , B32B2311/12 , B32B2311/22 , C04B2237/40 , C04B2237/403 , C04B2237/405 , G03F7/2039 , H05K1/0306 , H05K1/092 , H05K3/207 , H05K2203/0514 , Y10S430/168 , Y10T428/24926
摘要： A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the material remains on the ceramic sheet. The structure has a conductive patterned material which includes a photosensitive agent.
摘要翻译：在陶瓷片上形成导电图案的方法和结构将感光导电材料沉积在载体上并在材料上暴露出x射线能量的图案，并将载体和材料烧结到陶瓷片上，使得只有导电图案的材料残留在陶瓷片上。该结构具有包括感光剂的导电图案化材料。

77. 发明授权

US06579743B2 Chip packaging system and method using deposited diamond film 有权
公开(公告)号：US06579743B2
公开(公告)日：2003-06-17
申请号：US10041639
申请日：2002-01-07
申请人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
发明人： Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Tsorng-Dih Yuan
IPC分类号： H01L2100
CPC分类号： H01L23/473 , H01L23/3677 , H01L23/3732 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/051 , H01L2224/05548 , H01L2224/0557 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01019 , H01L2924/10253 , Y10S257/93 , H01L2924/00 , H01L2224/05599
摘要： A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

78. 发明授权

US5624869A Method of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogen 失效
标题翻译：用于提高使用铂或氮的硅化钴的热稳定性的多层半导体器件的膜的形成方法
公开(公告)号：US5624869A
公开(公告)日：1997-04-29
申请号：US226923
申请日：1994-04-13
申请人： Paul D. Agnello , Cyril Cabral, Jr. , Lawrence A. Clevenger , Matthew W. Copel , Francois M. d'Heurle , Qi-Zhong Hong
发明人： Paul D. Agnello , Cyril Cabral, Jr. , Lawrence A. Clevenger , Matthew W. Copel , Francois M. d'Heurle , Qi-Zhong Hong
IPC分类号： H01L21/28 , H01L21/265 , H01L21/285 , H01L21/336 , H01L29/78
CPC分类号： H01L21/28518 , Y10S438/934
摘要： A method and a device directed to the same, for stabilizing cobalt di-silicide/single crystal silicon, amorphous silicon, polycrystalline silicon, germanide/crystalline germanium, polycrystalline germanium structures or other semiconductor material structures so that high temperature processing steps (above 750.degree. C.) do not degrade the structural quality of the cobalt di-silicide/silicon structure. The steps of the method include forming a di-silicide or germanide by either reacting cobalt with the substrate material and/or the codeposition of the di-silicide or germanide on a substrate, adding a selective element, either platinum or nitrogen, into the cobalt and forming the di-silicide or germanide by a standard annealing treatment. Alternatively, the cobalt di-silicide or cobalt germanide can be formed after the formation of the di-silicide or germanide respectively. As a result, the upper limit of the annealing temperature at which the di-silicide or germanide will structurally degrade is increased.
摘要翻译：涉及其的方法和装置，用于稳定二硅化硅/单晶硅，非晶硅，多晶硅，锗化锗/结晶锗，多晶锗结构或其他半导体材料结构，使得高温处理步骤（高于750° C.）不会降低二硅化钴/硅结构的结构质量。该方法的步骤包括通过使钴与基底材料反应和/或二硅化物或锗化物在基底上共沉积形成二硅化物或锗化物，向铂中添加铂或氮的选择性元素并通过标准退火处理形成二硅化物或锗化物。另外也可以分别在二硅化物或锗化物形成之后形成二硅化钴或锗化钴。结果，二硅化物或锗化锗在结构上降解的退火温度的上限增加。

79. 发明授权

US5510295A Method for lowering the phase transformation temperature of a metal silicide 失效
标题翻译：降低金属硅化物的相变温度的方法
公开(公告)号：US5510295A
公开(公告)日：1996-04-23
申请号：US145921
申请日：1993-10-29
申请人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Francois M. d'Heurle , James M. E. Harper , Randy W. Mann , Glen L. Miles , Donald W. D. Rakowski
发明人： Cyril Cabral, Jr. , Lawrence A. Clevenger , Francois M. d'Heurle , James M. E. Harper , Randy W. Mann , Glen L. Miles , Donald W. D. Rakowski
IPC分类号： C23C20/02 , C30B1/02 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665 , Y10S148/04 , Y10S148/147
摘要： The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C. Optionally, the wafer is annealed following the step of disposing the refractory metal and prior to the step of depositing the precursory metal layer. Preferably, this annealing step is performed at a wafer temperature of at least about 900.degree. C.
摘要翻译：形成在半导体晶片上的硅层上形成的金属硅化物层的相变温度降低。首先，将难熔金属设置在硅层的表面附近，在覆盖难熔金属的层中沉积前体金属，并将晶片加热到足以从前体金属形成金属硅化物的温度。前体金属可以是难熔金属，优选为钛，钨或钴。硅层表面的难熔金属的浓度优选小于约1017原子/ cm3。难熔金属可以是Mo，Co，W，Ta，Nb，Ru或Cr，更优选为Mo或Co。用于形成硅化物的加热步骤在低于约700℃的温度下进行，更优选在约600℃至700℃之间。任选地，在沉积难熔金属的步骤之后，并且在沉积前体金属层的步骤之前，将晶片退火。优选地，该退火步骤在至少约900℃的晶片温度下进行。

80. 发明授权

US08921976B2 Using backside passive elements for multilevel 3D wafers alignment applications 有权
标题翻译：使用背面无源元件进行多层次3D晶圆校准应用
公开(公告)号：US08921976B2
公开(公告)日：2014-12-30
申请号：US13324791
申请日：2011-12-13
申请人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
发明人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
IPC分类号： H01L27/08 , H01L25/00 , H01L25/065 , H01L27/06 , H01L23/64 , H01L23/00
CPC分类号： H01L27/0694 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2223/6677 , H01L2224/02372 , H01L2224/0401 , H01L2224/05547 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2224/2919 , H01L2224/32145 , H01L2224/80357 , H01L2224/80805 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/01029 , H01L2924/01322 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/014 , H01L2924/00
摘要： Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.
摘要翻译：无源电路元件形成在两个集成电路晶片的表面。无源电路元件用于对准两个集成电路晶片以形成集成电路晶片叠层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式