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71. 发明申请

US20120091519A1 METHOD AND APPARATUS FOR IMPROVING CAPACITOR CAPACITANCE AND COMPATIBILITY 有权
标题翻译：用于提高电容器容量和兼容性的方法和装置
公开(公告)号：US20120091519A1
公开(公告)日：2012-04-19
申请号：US12905523
申请日：2010-10-15
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L27/108 , H01L21/02 , H01L29/92
CPC分类号： H01L23/5223 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底中的隔离结构，设置在隔离结构上的导电层，设置在隔离结构上的电容器，电容器包括顶电极，底电极和介于所述顶部电极和所述底部电极以及将所述导电层和所述底部电极电耦合的第一接触件，所述底部电极在至少两个面上基本接合所述第一接触。

72. 发明申请

US20100213572A1 Dual-Dielectric MIM Capacitors for System-on-Chip Applications 有权
标题翻译：用于片上系统应用的双电介质MIM电容器
公开(公告)号：US20100213572A1
公开(公告)日：2010-08-26
申请号：US12618021
申请日：2009-11-13
申请人： Kuo-Cheng Ching , Kuo-Chi Tu
发明人： Kuo-Cheng Ching , Kuo-Chi Tu
IPC分类号： H01L29/92
CPC分类号： H01L23/5223 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/11 , H01L27/1116 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively.
摘要翻译：集成电路结构包括具有第一区域和第二区域的芯片。在第一区域形成第一金属绝缘体金属（MIM）电容器。第一MIM电容器具有第一底部电极; 位于所述第一底部电极之上的第一顶部电极; 以及在所述第一底部电极和所述第一顶部电极之间并邻接所述第一电极绝缘体。第二MIM电容器在第二区域中，并且与第一MIM电容器基本一致。第二MIM电容器包括第二底部电极; 在所述第二底部电极上方的第二顶部电极; 以及在所述第二底部电极和所述第二顶部电极之间并邻接所述第二电极绝缘体。第二电容绝缘体与第一电容绝缘体不同。第一顶部电极和第一底部电极可以分别与第二顶部电极和第二底部电极同时形成。

73. 发明授权

US07262090B2 Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes 有权
标题翻译：随机存取存储器（RAM）电容器在浅沟槽隔离中，具有改善的电隔离到覆盖栅电极
公开(公告)号：US07262090B2
公开(公告)日：2007-08-28
申请号：US11223287
申请日：2005-09-09
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L21/31144 , H01L21/76237 , H01L21/823481 , H01L27/10835 , H01L27/10861 , H01L27/1087
摘要： A process for fabricating a novel random access memory (RAM) capacitor in a shallow trench isolation (STI) The method utilizes a novel node photoresist mask for plasma etching recesses in the STI that prevents plasma-etch-induced defects in the substrate. This novel photoresist mask is used to etch bottle-shaped recesses in the STI under a first hard mask. After forming bottom electrodes in the recesses and forming an interelectrode dielectric layer, a conducting layer is deposited sufficiently thick to fill the recesses and to form a planar surface, and a second hard mask is deposited. The conducting layer is patterned to form the capacitor top electrodes. This reduced topography results in reduced leakage currents when the gate electrodes are formed over the capacitor top electrodes.
摘要翻译：用于制造浅沟槽隔离（STI）中的新型随机存取存储器（RAM）电容器的方法该方法利用新颖的节点光刻胶掩模，用于STI中的等离子体蚀刻凹槽，以防止衬底中的等离子体蚀刻引起的缺陷。该新型光刻胶掩模用于蚀刻第一硬掩模下STI中的瓶形凹槽。在凹陷中形成底部电极并形成电极间电介质层之后，将导电层沉积得足够厚以填充凹部并形成平坦表面，并且沉积第二硬掩模。将导电层图案化以形成电容器顶部电极。当栅电极形成在电容器顶部电极上时，这种减小的形状导致减小的漏电流。

74. 发明授权

US07199423B2 Non-volatile memory technology compatible with 1T-RAM process 有权
标题翻译：非易失性存储器技术兼容1T-RAM过程
公开(公告)号：US07199423B2
公开(公告)日：2007-04-03
申请号：US11120118
申请日：2005-05-02
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11539
摘要： Methods of fabricating memory devices having non-volatile and volatile memory are provided. A substrate is provided, wherein the substrate has a non-volatile memory region and a volatile memory region. The non-volatile memory region has a storage device, such as a split-gate transistor, that is fabricated in substantially the same process steps as a storage capacitor of the volatile memory region. The reduction of process steps allow mixed memory to be fabricated in a cost effective manner.
摘要翻译：提供了制造具有非易失性和易失性存储器的存储器件的方法。提供了一种衬底，其中衬底具有非易失性存储区和易失性存储区。非易失性存储器区域具有以与易失性存储器区域的存储电容器基本相同的工艺步骤制造的存储器件，例如分离栅极晶体管。工艺步骤的减少允许以成本有效的方式制造混合存储器。

75. 发明授权

US07195970B2 Metal-insulator-metal capacitors 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US07195970B2
公开(公告)日：2007-03-27
申请号：US10811409
申请日：2004-03-26
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L27/148
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.
摘要翻译：提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。触点提供连接节点和形成在连接节点上方的组件之间的电连接。第二触点提供与顶部电极的电连接。

76. 发明授权

US07071509B2 Method of improving the top plate electrode stress inducting voids for 1T-RAM process 失效
标题翻译：改进1T-RAM工艺的顶板电极应力诱导空隙的方法
公开(公告)号：US07071509B2
公开(公告)日：2006-07-04
申请号：US11040039
申请日：2005-01-21
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/60 , H01L21/0276 , H01L27/10861 , H01L27/10891 , H01L27/11
摘要： A method for fabricating a capacitor with overlying transistor without stress-induced voids is described. A capacitor stack is provided overlying a substrate. A stress-balancing dielectric layer is deposited overlying the stack. An anti-reflective coating (ARC) layer is deposited overlying the stress-balancing layer. The stack is patterned to form the capacitors. Gate transistors are formed overlying the capacitors wherein the stress-balancing layer prevents formation of stress-induced voids during the thermal processes involved in forming the gate transistors.
摘要翻译：描述了一种制造具有不具有应力诱发空隙的上覆晶体管的电容器的方法。覆盖在基板上的电容器叠层被提供。叠层堆叠应力平衡介电层。沉积在应力平衡层上的抗反射涂层（ARC）层。图案化堆叠以形成电容器。形成覆盖电容器的栅极晶体管，其中应力平衡层在形成栅极晶体管的热处理期间阻止形成应力诱发的空隙。

77. 发明授权

US07030444B2 Space process to prevent the reverse tunneling in split gate flash 失效
标题翻译：空间过程，以防止分流门闪光中的反向隧道
公开(公告)号：US07030444B2
公开(公告)日：2006-04-18
申请号：US10786798
申请日：2004-02-25
申请人： Kuo-Chi Tu , Wen-Ting Chu , Yi-Shing Chang , Yi-Jiun Lin
发明人： Kuo-Chi Tu , Wen-Ting Chu , Yi-Shing Chang , Yi-Jiun Lin
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.
摘要翻译：公开了一种用于防止反向隧道的分裂门闪存单元结构。在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层，浮栅绝缘体层。栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

78. 发明申请

US20050258512A1 Topographically elevated microelectronic capacitor structure 审中-公开
标题翻译：地形高架微电子电容器结构
公开(公告)号：US20050258512A1
公开(公告)日：2005-11-24
申请号：US10851572
申请日：2004-05-21
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242 , H01L23/522 , H01L27/00 , H01L27/108
CPC分类号： H01L27/10894 , H01L23/5223 , H01L27/10814 , H01L27/10852 , H01L27/10897 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic product includes a capacitor structure spaced from a contact region within a substrate by a conductor stud layer and an interconnect layer formed upon the conductor stud layer. The interconnect layer may be further spaced from the capacitor structure by a contiguous conductor interconnect and conductor stud layer. The use of the interconnect layer and the contiguous conductor interconnect and conductor stud layer provide for flexible placement of the capacitor structure within the microelectronic product.
摘要翻译：微电子产品包括通过导体柱层与衬底内的接触区域间隔开的电容器结构，以及形成在导体柱层上的互连层。互连层可以通过连续的导体互连和导体柱层与电容器结构进一步间隔开。使用互连层和连续导体互连和导体柱层提供电容器结构在微电子产品内的柔性放置。

79. 发明申请

US20050212021A1 Metal-insulator-metal capacitors 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US20050212021A1
公开(公告)日：2005-09-29
申请号：US10811409
申请日：2004-03-26
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.
摘要翻译：提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。触点提供连接节点和形成在连接节点上方的组件之间的电连接。第二触点提供与顶部电极的电连接。

80. 发明申请

US20050124132A1 Self-aligned MIM capacitor process for embedded DRAM 有权
标题翻译：嵌入式DRAM的自对准MIM电容器工艺
公开(公告)号：US20050124132A1
公开(公告)日：2005-06-09
申请号：US11031717
申请日：2005-01-07
申请人： Kuo-Chi Tu
发明人： Kuo-Chi Tu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20 , H01L21/311
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10852 , H01L27/10897 , H01L28/91
摘要： A semiconductor device includes a group of capacitors and a trench. Each capacitor includes a first conductive material layer, a dielectric layer, and a second conductive material layer. The dielectric layer is located between the first and second conductive material layers. The first conductive material layer coats an inside surface of a cup-shaped opening formed in an insulating layer. The trench is formed in the insulating layer. The trench extends between and crosses each of the capacitors in the group. The dielectric layer and the second conductive material layer are formed over the first conductive material layer in the cup-shaped openings and over an inside surface of the trench. The second conductive material layer extends between the capacitors of the group via the trench. Also, the second conductive material layer forms top electrodes for the capacitors of the group.
摘要翻译：半导体器件包括一组电容器和沟槽。每个电容器包括第一导电材料层，电介质层和第二导电材料层。电介质层位于第一和第二导电材料层之间。第一导电材料层涂覆形成在绝缘层中的杯形开口的内表面。沟槽形成在绝缘层中。沟槽在组中每个电容器之间延伸并交叉。电介质层和第二导电材料层形成在杯形开口中的第一导电材料层上方和沟槽的内表面之上。第二导电材料层经由沟槽在组的电容器之间延伸。此外，第二导电材料层形成用于该组的电容器的顶部电极。

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