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1. 发明授权

US07195970B2 Metal-insulator-metal capacitors 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US07195970B2
公开(公告)日：2007-03-27
申请号：US10811409
申请日：2004-03-26
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L27/148
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.
摘要翻译：提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。触点提供连接节点和形成在连接节点上方的组件之间的电连接。第二触点提供与顶部电极的电连接。

2. 发明申请

US20050212021A1 Metal-insulator-metal capacitors 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US20050212021A1
公开(公告)日：2005-09-29
申请号：US10811409
申请日：2004-03-26
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.
摘要翻译：提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。触点提供连接节点和形成在连接节点上方的组件之间的电连接。第二触点提供与顶部电极的电连接。

3. 发明申请

US20070138531A1 Metal-insulator-metal capacitors 有权
公开(公告)号：US20070138531A1
公开(公告)日：2007-06-21
申请号：US11704088
申请日：2007-02-08
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.

4. 发明授权

US07557399B2 Metal-insulator-metal capacitors 有权
标题翻译：金属绝缘体金属电容器
公开(公告)号：US07557399B2
公开(公告)日：2009-07-07
申请号：US11704088
申请日：2007-02-08
申请人： Kuo-Chi Tu , Wai-Yi Lien
发明人： Kuo-Chi Tu , Wai-Yi Lien
IPC分类号： H01L31/119
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10852 , H01L27/10894 , H01L28/55 , H01L28/65
摘要： A metal-insulator-metal (MIM) capacitor is provided. The bottom electrode of the MIM capacitor is electrically connected to a connection node. The connection node may be, for example, a contact formed in an interlayer dielectric, a polysilicon connection node, a doped polysilicon or silicon region, or the like. A contact provides an electrical connection between the connection node and components formed above the connection node. A second contact provides an electrical connection to the top electrode.
摘要翻译：提供金属绝缘体金属（MIM）电容器。 MIM电容器的底部电极电连接到连接节点。连接节点可以是例如形成在层间电介质中的接触，多晶硅连接节点，掺杂多晶硅或硅区域等。触点提供连接节点和形成在连接节点上方的组件之间的电连接。第二触点提供与顶部电极的电连接。

5. 发明授权

US09202914B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09202914B2
公开(公告)日：2015-12-01
申请号：US13419530
申请日：2012-03-14
申请人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
发明人： Hsin-Ming Hou , Yu-Cheng Tung , Ji-Fu Kung , Wai-Yi Lien , Ming-Tsung Chen
IPC分类号： H01L29/78 , H01L21/336 , H01L31/072 , H01L29/12 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78 , H01L21/76224 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device including a substrate, a plurality of isolation structures, at least a gate structure, a plurality of dummy gate structures and a plurality of epitaxial structures is provided. The substrate has an active area defined by the isolation structures disposed within the substrate. That is, the active area is defined between the isolation structures. The gate structure is disposed on the substrate and located within the active area. The dummy gate structures are disposed on the substrate and located out of the active area. The edge of each dummy gate structure is separated from the boundary of the active area with a distance smaller than 135 angstroms. The epitaxial structures are disposed within the active area and in a portion of the substrate on two sides of the gate structure. The invention also provided a method for fabricating semiconductor device.
摘要翻译：提供了包括衬底，多个隔离结构，至少栅极结构，多个虚拟栅极结构和多个外延结构的半导体器件。衬底具有由设置在衬底内的隔离结构限定的有源区域。也就是说，在隔离结构之间限定有源区。栅极结构设置在基板上并且位于有源区域内。虚拟栅极结构设置在基板上并且位于有源区域之外。每个虚拟栅极结构的边缘与有效区域的边界分开，距离小于135埃。外延结构被布置在栅极结构的两侧的有源区域内和衬底的一部分中。本发明还提供了一种制造半导体器件的方法。

6. 发明授权

US07537982B2 Method and structure for isolating substrate noise 有权
标题翻译：隔离衬底噪声的方法和结构
公开(公告)号：US07537982B2
公开(公告)日：2009-05-26
申请号：US11972482
申请日：2008-01-10
申请人： Wai-Yi Lien , Denny Duan-lee Tang
发明人： Wai-Yi Lien , Denny Duan-lee Tang
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L21/263 , H01L21/761
摘要： An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit region and a second circuit region. Two guard rings are formed along the semi-insulating region, each on a side. A backside semi-insulating region is formed through proton bombardment from the back surface of the substrate into the substrate. The backside semi-insulating region is preferably connected with the semi-insulating region. A grounded guard layer is preferably formed on the backside semi-insulating region.
摘要翻译：提供了用于隔离衬底噪声的集成电路结构及其形成方法。在本发明的优选实施例中，使用质子轰击在第一电路区域和第二电路区域之间的衬底中形成半绝缘区域。沿着半绝缘区域形成两个保护环，每个在一侧。通过从衬底的背面进入衬底的质子轰击形成背面半绝缘区域。背面半绝缘区域优选与半绝缘区域连接。优选地，在背面半绝缘区域上形成接地保护层。

7. 发明授权

US07492018B2 Isolating substrate noise by forming semi-insulating regions 有权
标题翻译：通过形成半绝缘区域隔离衬底噪声
公开(公告)号：US07492018B2
公开(公告)日：2009-02-17
申请号：US11089186
申请日：2005-03-24
申请人： Wai-Yi Lien , Denny Duan-lee Tang
发明人： Wai-Yi Lien , Denny Duan-lee Tang
IPC分类号： H01L29/76 , H01L29/47
CPC分类号： H01L21/263 , H01L21/761
摘要： An integrated circuit structure for isolating substrate noise and a method of forming the same are provided. In the preferred embodiment of the present invention, a semi-insulating region is formed using proton bombardment in a substrate between a first circuit region and a second circuit region. Two guard rings are formed along the semi-insulating region, each on a side. A backside semi-insulating region is formed through proton bombardment from the back surface of the substrate into the substrate. The backside semi-insulating region is preferably connected with the semi-insulating region. A grounded guard layer is preferably formed on the backside semi-insulating region.
摘要翻译：提供了用于隔离衬底噪声的集成电路结构及其形成方法。在本发明的优选实施例中，使用质子轰击在第一电路区域和第二电路区域之间的衬底中形成半绝缘区域。沿着半绝缘区域形成两个保护环，每个在一侧。通过从衬底的背面进入衬底的质子轰击形成背面半绝缘区域。背面半绝缘区域优选与半绝缘区域连接。优选地，在背面半绝缘区域上形成接地保护层。

8. 发明授权

US06888063B1 Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling 失效
标题翻译：在射频集成电路中提供屏蔽的装置和方法，以减少噪声耦合
公开(公告)号：US06888063B1
公开(公告)日：2005-05-03
申请号：US10823874
申请日：2004-04-14
申请人： Wai-Yi Lien , Chung-Long Chang , Jyh-Chyurn Guo , John Chern
发明人： Wai-Yi Lien , Chung-Long Chang , Jyh-Chyurn Guo , John Chern
IPC分类号： H01L21/82 , H01L23/522 , H01L23/58 , H01L27/02 , H05K9/00
CPC分类号： H01L23/585 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.
摘要翻译：公开了一种具有用于最小化RF无源部件之间的耦合的屏蔽结构和用于有源部件的导电布线的半导体射频（RF）装置。在一个示例中，该装置包括形成在RF无源部件和导电布线之间的至少一个屏蔽层。屏蔽层包括至少一个开口。在另一示例中，可以使用第二屏蔽层。第二屏蔽层也可以具有开口，并且第一和第二屏蔽层中的开口可以彼此偏移。第一和第二屏蔽层可以通过保护环彼此连接，并且还可以连接到公共电压电位。

9. 发明授权

US06878964B1 Ground-signal-ground pad layout for device tester structure 有权
标题翻译：接地信号接地板布局用于器件测试仪结构
公开(公告)号：US06878964B1
公开(公告)日：2005-04-12
申请号：US10672608
申请日：2003-09-26
申请人： Wai-Yi Lien , Jyh-Chyurn Guo
发明人： Wai-Yi Lien , Jyh-Chyurn Guo
IPC分类号： H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L2924/3011
摘要： A tester for a semiconductor device is provided, which includes a bottom ground pad structure, an intermediate ground pad structure, and a top layer. The bottom ground pad structure is electrically connected to a substrate. The bottom ground pad structure includes a bottom signal shield plate. The intermediate ground pad structure is electrically connected to the bottom ground pad structure. The intermediate ground pad structure is located over the bottom ground pad structure. The top layer is located over the intermediate ground pad structure. The top layer includes a device under test (DUT), a ground probe pad, a signal probe pad, and leads. The DUT is electrically connected to the ground probe pad and the signal probe pad via the leads. The ground probe pad is electrically connected to the intermediate ground pad structure. The signal probe pad is located over the bottom signal shield plate.
摘要翻译：提供了一种用于半导体器件的测试器，其包括底部接地焊盘结构，中间接地焊盘结构和顶层。底部接地焊盘结构电连接到基板。底部接地焊盘结构包括底部信号屏蔽板。中间接地焊盘结构电连接到底部接地焊盘结构。中间接地焊盘结构位于底部接地焊盘结构之上。顶层位于中间接地焊盘结构之上。顶层包括被测器件（DUT），接地探针焊盘，信号探针焊盘和引线。 DUT通过引线电连接到接地探针焊盘和信号探针焊盘。接地探针焊盘电连接到中间接地焊盘结构。信号探针垫位于底部信号屏蔽板上。

10. 发明申请

US20120256273A1 METHOD OF UNIFYING DEVICE PERFORMANCE WITHIN DIE 审中-公开
标题翻译：在DIE中统一设备性能的方法
公开(公告)号：US20120256273A1
公开(公告)日：2012-10-11
申请号：US13228455
申请日：2011-09-09
申请人： Yu-Ho Chiang , Ming-Tsung Chen , Wai-Yi Lien , Chih-Kai Hsu , Chun-Liang Hou
发明人： Yu-Ho Chiang , Ming-Tsung Chen , Wai-Yi Lien , Chih-Kai Hsu , Chun-Liang Hou
IPC分类号： H01L29/06 , H01L21/765 , H01L21/762
CPC分类号： H01L27/0207
摘要： A method of unifying device performance within an integrated circuit die includes providing a layout of an integrated circuit die with multiple functional circuit blocks; filling a field between the multiple functional circuit blocks with dummy diffusion patterns; and filling the field between the multiple functional circuit blocks with dummy gate patterns such that the dummy gate patterns and the dummy diffusion patterns are completely overlapped.
摘要翻译：在集成电路管芯内统一器件性能的方法包括：提供具有多个功能电路块的集成电路管芯的布局; 用虚拟扩散图案填充多个功能电路块之间的场; 并且用虚拟栅极图案填充多个功能电路块之间的场，使得虚拟栅极图案和虚拟扩散图案完全重叠。

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