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71. 发明授权

US06670681B2 Semiconductor structures 有权
标题翻译：半导体结构
公开(公告)号：US06670681B2
公开(公告)日：2003-12-30
申请号：US10341925
申请日：2003-01-13
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L2976
CPC分类号： H01L21/823878 , H01L21/266 , H01L21/823842
摘要： A method of implanting dopants into a semiconductor structure wherein a lateral periphery of a photoresist mask is shifted after implanting a first dopant and prior to implanting a second dopant. The invention also includes semiconductor structures having two doped regions of a semiconductive material separated by a region less heavily doped than the doped regions.
摘要翻译：将掺杂剂注入到半导体结构中的方法，其中在注入第一掺杂剂之后并且在注入第二掺杂剂之前光致抗蚀剂掩模的横向周边发生偏移。本发明还包括具有半导体材料的两个掺杂区域的半导体结构，所述半导体材料由掺杂区域的掺杂区域分开。

72. 发明授权

US06639319B2 Conductive structure in an integrated circuit 有权
公开(公告)号：US06639319B2
公开(公告)日：2003-10-28
申请号：US09953675
申请日：2001-09-17
申请人： Jigish D. Trivedi , Ravi Iyer
发明人： Jigish D. Trivedi , Ravi Iyer
IPC分类号： H01L2348
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.

73. 发明授权

US06562689B1 Non-ion-implanted resistive silicon oxynitride films as resistors 失效
标题翻译：非离子注入电阻氮氧化硅薄膜作为电阻
公开(公告)号：US06562689B1
公开(公告)日：2003-05-13
申请号：US09549823
申请日：2000-04-14
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01C7/006 , H01C17/08 , H01L27/0802 , H01L27/1112 , Y10S257/904 , Y10S438/954
摘要： The present disclosure is directed to the use of non-ion-implanted silicon oxynitride films as resistive elements. Such films have been traditionally used in semiconductor processing as antireflective coatings, but their utility as highly resistive circuit elements has heretofore not been realized. Such films find specific utility when used as the load resistors in a 4-T SRAM cell.
摘要翻译：本公开涉及使用非离子注入的氮氧化硅膜作为电阻元件。这种薄膜传统上用于半导体加工中作为抗反射涂层，但是它们作为高电阻电路元件的用途迄今尚未实现。当用作4-T SRAM单元中的负载电阻时，这种电影具有特殊的用途。

74. 发明授权

US06548383B1 Twin well methods of forming CMOS integrated circuitry 有权
标题翻译：双阱形成CMOS集成电路的方法
公开(公告)号：US06548383B1
公开(公告)日：2003-04-15
申请号：US09441912
申请日：1999-11-17
申请人： Jigish D. Trivedi , Zhongze Wang , Michael P. Violette
发明人： Jigish D. Trivedi , Zhongze Wang , Michael P. Violette
IPC分类号： H01L21425
CPC分类号： H01L21/823892
摘要： In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps. In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.
摘要翻译：根据本发明的一个方面，形成具有第一和第二导电类型栅极的CMOS集成电路的双阱方法包括：导电第一导电类型阱注入，第二导电类型阱注入，第一导电型栅极注入和使用不超过两个掩模步骤的第二导电类型栅极注入。在本发明的另一方面，形成具有第一和第二导电类型晶体管栅极的CMOS集成电路的双阱法包括在公共掩模步骤中传导第一导电类型阱注入和第二导电类型栅极注入。

75. 发明授权

US06544881B2 Stacked local interconnect structure and method of fabricating same 有权
公开(公告)号：US06544881B2
公开(公告)日：2003-04-08
申请号：US10076792
申请日：2002-02-14
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L214763
CPC分类号： H01L21/76895 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A method of forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

76. 发明授权

US06535413B1 Method of selectively forming local interconnects using design rules 有权
公开(公告)号：US06535413B1
公开(公告)日：2003-03-18
申请号：US09652070
申请日：2000-08-31
申请人： Todd Abbott , Jigish D. Trivedi , Mike Violette , Chuck Dennison
发明人： Todd Abbott , Jigish D. Trivedi , Mike Violette , Chuck Dennison
IPC分类号： H01L2334
CPC分类号： H01L21/76897 , H01L21/76889 , H01L21/76895 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

77. 发明授权

US06440817B2 Methods of forming integrated circuitry 有权
标题翻译：形成集成电路的方法
公开(公告)号：US06440817B2
公开(公告)日：2002-08-27
申请号：US09960119
申请日：2001-09-21
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L2176
CPC分类号： H01L21/76897 , H01L21/76232 , H01L21/823475 , H01L21/823481
摘要： A method of forming integrated circuitry includes forming a shallow junction region within semiconductor material. An anisotropically etched sidewall spacer of a first material comprising at least one of Al2O3 and Ta2O5 is formed laterally proximate the shallow junction region. Trench isolation of a second material different from the first material is formed laterally proximate the anisotropically etched sidewall spacer, with the anisotropically etched sidewall spacer being received intermediate the shallow junction region and the trench isolation of the second material. Other aspects are contemplated.
摘要翻译：形成集成电路的方法包括在半导体材料内形成浅结区域。包含Al 2 O 3和Ta 2 O 5中的至少一种的第一材料的各向异性蚀刻的侧壁间隔物横向靠近浅结区域形成。不同于第一材料的第二材料的沟槽隔离在各向异性蚀刻的侧壁间隔件的横向附近形成，各向异性蚀刻的侧壁间隔件被接收在浅结区域的中间和第二材料的沟槽隔离之间。考虑其他方面。

78. 发明授权

US06355966B1 Methods of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry 失效
标题翻译：形成集成电路隔离沟槽的方法，形成集成电路的方法和集成电路
公开(公告)号：US06355966B1
公开(公告)日：2002-03-12
申请号：US09800591
申请日：2001-03-06
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L3100
CPC分类号： H01L21/76897 , H01L21/76232 , H01L21/823475 , H01L21/823481
摘要： A method of forming an integrated circuitry trench isolation region includes etching a first portion of an isolation trench into a semiconductor substrate. The first portion has laterally opposing sidewalls and a trench base extending therebetween. A second portion of the isolation trench is etched into the semiconductor substrate through only a portion of the first portion trench base. After the second etching, insulative trench isolation material is deposited to be received within the first and second portions of the isolation trench. In one implementation, a method of forming integrated circuitry includes forming a trench isolation region and an adjacent shallow junction region in a semiconductor substrate. The trench isolation region includes a sidewall adjacent the shallow junction region, the trench isolation region comprising at least two insulative trench isolation materials. A first of the materials is received over at least an outermost portion of the sidewall and a second of the materials is received adjacent the first, with the first material being received between the junction isolation region and the second material. A covering insulative material is formed over the trench isolation region and the shallow junction region. A contact opening is etched through the covering insulative material to the shallow junction region and the trench isolation region substantially selective to etch the covering insulative material relative to the first trench isolation material within the trench isolation region. Integrated circuitry independent of the method of fabrication is contemplated.
摘要翻译：形成集成电路沟槽隔离区域的方法包括将隔离沟槽的第一部分蚀刻成半导体衬底。第一部分具有横向相对的侧壁和在其间延伸的沟槽基底。隔离沟槽的第二部分仅通过第一部分沟槽基底的一部分被蚀刻到半导体衬底中。在第二蚀刻之后，沉积沟槽隔离材料被沉积在隔离沟槽的第一和第二部分内。在一个实现中，形成集成电路的方法包括在半导体衬底中形成沟槽隔离区域和相邻的浅结区域。沟槽隔离区域包括邻近浅结区域的侧壁，沟槽隔离区域包括至少两个绝缘沟槽隔离材料。材料中的第一种被容纳在侧壁的至少最外侧部分上，并且第二材料被接收在第一材料附近，第一材料被接纳在结隔离区域和第二材料之间。在沟槽隔离区域和浅结区域上形成覆盖绝缘材料。通过覆盖绝缘材料将接触开口蚀刻到浅结区域和沟槽隔离区域，其基本上选择性地相对于沟槽隔离区域内的第一沟槽隔离材料蚀刻覆盖绝缘材料。考虑了与制造方法无关的集成电路。

79. 发明授权

US08003526B2 Low resistance metal silicide local interconnects and a method of making 有权
标题翻译：低电阻金属硅化物局部互连和制造方法
公开(公告)号：US08003526B2
公开(公告)日：2011-08-23
申请号：US12720716
申请日：2010-03-10
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.
摘要翻译：用于形成局部互连的工艺包括在半导体层上施加一层金属。金属硅化物层形成在金属层上。将金属硅化物层图案化以限定局部互连的边界。金属硅化物与金属层反应形成复合结构。复合结构包括金属硅化物，由金属硅化物形成为硅的另一金属硅化物与金属的下层反应，金属硅化物与来自金属和金属的金属的金属间化合物反应。复合结构残留作为局部互连，去除未反应的金属层。

80. 发明申请

US20100167528A1 LOW RESISTANCE METAL SILICIDE LOCAL INTERCONNECTS AND A METHOD OF MAKING 有权
标题翻译：低电阻金属硅化物局部互连及其制备方法
公开(公告)号：US20100167528A1
公开(公告)日：2010-07-01
申请号：US12720716
申请日：2010-03-10
申请人： Jigish D. Trivedi
发明人： Jigish D. Trivedi
IPC分类号： H01L21/768
CPC分类号： H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.
摘要翻译：用于形成局部互连的工艺包括在半导体层上施加一层金属。金属硅化物层形成在金属层上。将金属硅化物层图案化以限定局部互连的边界。金属硅化物与金属层反应形成复合结构。复合结构包括金属硅化物，由金属硅化物形成为硅的另一金属硅化物与金属的下层反应，金属硅化物与来自金属和金属的金属的金属间化合物反应。复合结构残留作为局部互连，去除未反应的金属层。

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