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71. 发明授权

US5933717A Vertical transistor interconnect structure and fabrication method thereof 失效
标题翻译：垂直晶体管互连结构及其制造方法
公开(公告)号：US5933717A
公开(公告)日：1999-08-03
申请号：US811381
申请日：1997-03-04
申请人： Frederick N. Hause , Mark I. Gardner
发明人： Frederick N. Hause , Mark I. Gardner
IPC分类号： H01L21/768 , H01L21/8234 , H01L27/088 , H01L21/8238
CPC分类号： H01L21/823487 , H01L21/768 , H01L27/088
摘要： It has been discovered that improvements in the compactness and performance of integrated circuit devices are gained through the fabrication of vertical transistors for which channel sizes are determined by the accuracy of etch techniques rather than the resolution of photolithographic techniques. Etching in the vertical dimension is precisely controlled to resolutions of about 0.1 .mu.m while advanced photolithographic techniques in a volume production environment achieve resolutions of 0.25 .mu.m. Interconnect structures for connecting to high density vertical transistors are formed by depositing metal into the trenches etched during fabrication of the vertical transistors. A method of fabricating an integrated circuit includes etching a trench with a sidewall in a substrate wafer and forming a vertical transistor on the sidewall. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The method of fabricating an integrated circuit further includes forming an interconnect in the trench coupled to the vertical transistor. An integrated circuit includes a substrate wafer having a trench with a sidewall and a vertical transistor formed on the sidewall of the trench. The vertical transistor has a drain, a channel and a source doped at a series of vertical depths in the substrate wafer. The vertical transistor has a gate coupled to the sidewall adjacent to the drain, the channel, and the source. The integrated circuit further includes an interconnect in the trench coupled to the vertical transistor.
摘要翻译：已经发现，通过制造垂直晶体管来获得集成电路器件的紧凑性和性能的改进，其中沟道尺寸由蚀刻技术的精度而不是光刻技术的分辨率确定。在垂直尺寸上的蚀刻被精确地控制在约0.1μm的分辨率上，而在批量生产环境中的先进的光刻技术实现了0.25μm的分辨率。用于连接到高密度垂直晶体管的互连结构通过在垂直晶体管的制造过程中蚀刻的沟槽中沉积金属而形成。制造集成电路的方法包括：在衬底晶片中蚀刻具有侧壁的沟槽，并在侧壁上形成垂直晶体管。垂直晶体管具有在衬底晶片中的一系列垂直深度处掺杂的漏极，沟道和源极。晶体管具有与漏极，沟道和源极相邻的侧壁耦合的栅极。制造集成电路的方法还包括在与垂直晶体管耦合的沟槽中形成互连。集成电路包括具有侧壁沟槽和形成在沟槽侧壁上的垂直晶体管的衬底晶片。垂直晶体管具有在衬底晶片中的一系列垂直深度处掺杂的漏极，沟道和源极。垂直晶体管具有与漏极，沟道和源极相邻的侧壁耦合的栅极。该集成电路还包括在与该垂直晶体管耦合的沟槽中的互连。

72. 发明授权

US5923984A Method of making enhancement-mode and depletion-mode IGFETS with different gate materials 失效
标题翻译：使用不同栅极材料制作增强型和耗尽型IGFETS的方法
公开(公告)号：US5923984A
公开(公告)日：1999-07-13
申请号：US844923
申请日：1997-04-21
申请人： Mark I. Gardner , Frederick N. Hause
发明人： Mark I. Gardner , Frederick N. Hause
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/336
CPC分类号： H01L27/0883 , H01L21/82345
摘要： A method of making enhancement-mode and depletion-mode IGFETs with different gate materials is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a first gate composed of a first gate material over the first device region, forming a second gate composed of a second gate material over the second device region, implanting a dopant into the substrate and into the first and second gates to implant source and drain regions in the first device region and source and drain regions in the second device region, and transferring the dopant through the first gate into a first channel region in the first device region beneath the first gate without transferring essentially any of the dopant through the second gate into a second channel region in the second device region beneath the second gate, thereby providing depletion-mode doping in the first channel region while retaining enhancement-mode doping in the second channel region. The dopant can be implanted through the first gate into the first channel region. Alternatively, the dopant can be implanted into the first gate but not the first channel region and then diffused from the first gate into the first channel region. Advantageously, by employing different gate materials, a single implant step can be used to provide lightly doped source/drain regions for enhancement and depletion-mode IGFETs as well as depletion-mode doping for channel regions of depletion-mode IGFETs (with gates composed of the first gate material) while retaining enhancement-mode doping for channel regions of enhancement-mode IGFETs (with gates composed of the second gate material).
摘要翻译：公开了一种利用不同栅极材料制造增强型和耗尽型IGFET的方法。该方法包括向半导体衬底提供第一和第二器件区域，在第一器件区域上形成由第一栅极材料构成的第一栅极，在第二器件区域上形成由第二栅极材料构成的第二栅极，将掺杂剂注入衬底并进入第一和第二栅极，以在第一器件区域中注入源极和漏极区域，并在第二器件区域中注入源极和漏极区域，并将掺杂剂通过第一栅极转移到第一器件区域内的第一沟道区域中第一栅极，而不将基本上任何掺杂剂通过第二栅极转移到第二栅极下面的第二器件区域中的第二沟道区域中，从而在第一沟道区域中提供耗尽模式掺杂，同时在第二沟道中保持增强模式掺杂地区。掺杂剂可以通过第一栅极注入第一沟道区。或者，可以将掺杂剂注入第一栅极而不是第一沟道区，然后从第一栅极扩散到第一沟道区。有利地，通过采用不同的栅极材料，可以使用单个注入步骤来提供用于增强和耗尽型IGFET的轻掺杂源极/漏极区域以及耗尽型IGFET的沟道区域的耗尽模式掺杂（栅极由第一栅极材料），同时保持增强型IGFET（具有由第二栅极材料构成的栅极）的沟道区域的增强型掺杂。

73. 发明授权

US5923980A Trench transistor with localized source/drain regions implanted through voids in trench 失效
标题翻译：具有通过沟槽中的空隙注入局部源/漏区的沟槽晶体管
公开(公告)号：US5923980A
公开(公告)日：1999-07-13
申请号：US739592
申请日：1996-10-30
申请人： Mark I. Gardner , H. Jim Fulford, Jr. , Frederick N. Hause
发明人： Mark I. Gardner , H. Jim Fulford, Jr. , Frederick N. Hause
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78 , H01L21/00 , H01L21/265
CPC分类号： H01L29/66621 , H01L21/28114 , H01L29/42376 , H01L29/7834
摘要： A method of forming an IGFET includes forming a trench in a substrate, forming spacers on opposing sidewalls of the trench, forming a gate insulator on a bottom surface of the trench between the spacers, forming a gate electrode on the gate insulator and the spacers, removing at least portions of the spacers to form voids in the trench after forming the gate electrode, implanting localized source and drain regions through the voids and through the bottom surface of the trench outside the gate electrode, and forming a source and drain in the substrate that include the localized source and drain regions adjacent to the bottom surface of the trench. The localized source and drain regions provide accurately positioned channel junctions beneath the trench. Furthermore, the dopant concentration of the localized source and drain regions is controlled by the amount of the spacers, if any, left intact when the localized source and drain regions are implanted after removing the portions of the spacers.
摘要翻译：形成IGFET的方法包括在衬底中形成沟槽，在沟槽的相对侧壁上形成间隔物，在间隔物之间的沟槽的底表面上形成栅极绝缘体，在栅极绝缘体上形成栅电极和间隔物，在形成栅电极之后移除间隔物的至少部分以在沟槽中形成空隙，通过空隙注入局部源极和漏极区域，并通过栅电极外部的沟槽的底表面，以及在衬底中形成源极和漏极其包括与沟槽的底表面相邻的局部源极和漏极区域。局部源极和漏极区域在沟槽下方提供精确定位的通道结。此外，当在去除间隔物的部分之后植入局部源极和漏极区域时，局部源极和漏极区域的掺杂剂浓度受到间隔物的量（如果有的话）保持不变。

74. 发明授权

US5918126A Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size 失效
标题翻译：使用偏置差分制造具有不同器件密度的器件的集成电路的制造方法，以形成具有均匀尺寸的器件
公开(公告)号：US5918126A
公开(公告)日：1999-06-29
申请号：US805796
申请日：1997-02-25
申请人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： H. Jim Fulford, Jr. , Robert Dawson , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/3213 , H01L21/8234
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/823456
摘要： It has been discovered that different pattern densities that occur in conventional lithography produce a different final etch polysilicon gate width in high density (dense) regions of polysilicon gates as compared to low density (isolated) polysilicon gate regions. The final etch polysilicon gate width for a dense region is smaller by a predictable distance relative to the final etch polysilicon gate width for an isolated region. For example, a typical dense region has a final etch polysilicon gate width that is approximately 0.05 .mu.m smaller relative to the final etch polysilicon gate width of isolated regions having a channel length of 0.35 .mu.m. A biasing technique is employed for a polysilicon masking reticle in which the reticle is biased differently in regions of isolated polysilicon gates in comparison to regions of dense polysilicon gates. More specifically, in one embodiment the polysilicon masking reticle is increased in size in regions of high density polysilicon gates in comparison to regions of isolated polysilicon gates. In another embodiment, the reticle in regions of isolated polysilicon gates is sized normally but increased in size in regions of high density polysilicon gates. Following photomasking and etching, substantially identical polysilicon lengths are achieved in the isolated and dense gate regions.
摘要翻译：已经发现，与低密度（隔离）多晶硅栅极区域相比，在常规光刻中发生的不同图案密度在多晶硅栅极的高密度（密集）区域中产生不同的最终蚀刻多晶硅栅极宽度。用于密集区域的最终蚀刻多晶硅栅极宽度相对于隔离区域的最终蚀刻多晶硅栅极宽度可预测的距离较小。例如，典型的密集区域具有最终蚀刻多晶硅栅极宽度，相对于沟道长度为0.35μm的隔离区域的最终蚀刻多晶硅栅极宽度大约为0.05μm。对于多晶硅掩模掩模版采用偏置技术，其中与致密多晶硅栅极的区域相比，掩模版在隔离多晶硅栅极的区域中被不同地偏置。更具体地，在一个实施例中，与隔离多晶硅栅极的区域相比，多晶硅掩模掩模版的尺寸在高密度多晶硅栅极的区域中增加。在另一个实施例中，隔离多晶硅栅极的区域中的掩模版尺寸正常，但在高密度多晶硅栅极的区域中的尺寸增大。在光掩模和蚀刻之后，在隔离和密集的栅极区域中实现了基本相同的多晶硅长度。

75. 发明授权

US5851891A IGFET method of forming with silicide contact on ultra-thin gate 失效
标题翻译： IGFET在超薄栅极上与硅化物接触形成的方法
公开(公告)号：US5851891A
公开(公告)日：1998-12-22
申请号：US837521
申请日：1997-04-21
申请人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/6659 , H01L21/28052 , H01L29/4933 , H01L29/665
摘要： An IGFET with a silicide contact on an ultra-thin gate is disclosed. A method of forming the IGFET includes forming a gate over a semiconductor substrate, forming a source and a drain in the substrate, depositing a contact material over the gate, and reacting the contact material with the gate to form a silicide contact on the gate and consume at least one-half of the gate. By consuming such a large amount of the gate, a relatively thin gate can be converted into an ultra-thin gate with a thickness on the order of 100 to 200 angstroms. Preferably, the bottom surface of the gate is essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes a peak concentration of a dopant in the gate towards the substrate so that a heavy concentration of the dopant is pushed to the bottom surface of the gate without being pushed into the substrate. As exemplary materials, the contact material is a refractory metal such as titanium, the gate is polysilicon, and the dopant is arsenic.
摘要翻译：公开了一种在超薄栅极上具有硅化物接触的IGFET。形成IGFET的方法包括在半导体衬底上形成栅极，在衬底中形成源极和漏极，在栅极上沉积接触材料，并使接触材料与栅极反应以在栅极上形成硅化物接触，以及消耗至少一半的门。通过消耗大量的栅极，可以将相对薄的栅极转换成厚度在100至200埃左右的超薄栅极。优选地，栅极的底表面在使接触材料与栅极反应之前基本上是未掺杂的，并且使接触材料与栅极反应将栅极中的掺杂剂的峰值浓度推向衬底，使得掺杂剂的重浓度为被推入门的底表面而不被推入基板。作为示例性材料，接触材料是诸如钛的难熔金属，栅极是多晶硅，掺杂剂是砷。

76. 发明授权

US5849622A Method of forming a source implant at a contact masking step of a process flow 失效
标题翻译：在工艺流程的接触掩蔽步骤处形成源植入物的方法
公开(公告)号：US5849622A
公开(公告)日：1998-12-15
申请号：US812555
申请日：1997-03-07
申请人： Frederick N. Hause , Mark I. Gardner
发明人： Frederick N. Hause , Mark I. Gardner
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814
摘要： In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source implant of the dopant species having a the higher diffusivity is advantageously delayed until a contact masking process step. By delaying the dopant species having the higher diffusivity, depletion of the dopant by subsequent annealing steps is avoided. P MOSFETs formed using a high diffusivity boron implant species in an integrated circuit including both P MOSFETs and N MOSFET are fabricated with no source implant in the source regions during formation of the gate electrodes and sidewall spaces. Once the gate and spacer structures on the surface of a substrate wafer are complete and a contact masking step is performed for patterning contact vias, typically in preparation for contact metallization, contact vias are cut to the surface of the substrate and the substrate in the source area exposed by the vias is implanted with the source dopant. A method of fabricating an integrated circuit includes forming a lightly-doped drain(LDD) MOSFET structure prior to source/drain doping. The LDD MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate, and implanting a source implant through the contact via into the source of the LDD MOSFET structure.
摘要翻译：在具有N个MOSFET和P MOSFET的集成电路的制造中，其中相应的N型物质和P型物质具有基本上不同的扩散率，有利地延迟具有较高扩散率的掺杂物种类的源注入直到接触掩蔽工艺步骤。通过延迟具有较高扩散率的掺杂物种，避免了后续退火步骤对掺杂剂的消耗。在包括P MOSFET和N MOSFET的集成电路中使用高扩散性硼注入物形成的P MOSFET在栅电极和侧壁空间的形成期间在源极区域中没有源注入被制造。一旦衬底晶片表面上的栅极和间隔物结构完整，并且执行接触掩模步骤以对通常用于接触金属化的接触通孔进行图形化，则接触通孔被切割到衬底的表面，并且源极中的衬底通过通孔曝光的区域被注入源掺杂剂。制造集成电路的方法包括在源极/漏极掺杂之前形成轻掺杂漏极（LDD）MOSFET结构。 LDD MOSFET结构包括形成在栅极氧化物层上的衬底上的栅极，形成在栅极侧面的间隔物，源极区中的衬底的LDD掺杂和与栅极自对准的漏极区。该方法还包括在衬底和LDD MOSFET结构之上形成氧化物层，将接触通孔穿过氧化物层切割到栅极和间隔物附近的衬底表面，并邻接衬底的源极区域，并植入源极植入通过接触通孔进入LDD MOSFET结构的源极。

77. 发明授权

US5840451A Individually controllable radiation sources for providing an image pattern in a photolithographic system 失效
标题翻译：用于在光刻系统中提供图像图案的可单独控制的辐射源
公开(公告)号：US5840451A
公开(公告)日：1998-11-24
申请号：US760029
申请日：1996-12-04
申请人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
发明人： Bradley T. Moore , Robert Dawson , H. Jim Fulford, Jr. , Mark I. Gardner , Frederick N. Hause , Mark W. Michael , Derick J. Wristers
IPC分类号： G03F7/20 , G03F9/00
CPC分类号： G03F7/70391 , G03F7/20 , Y10S430/146 , Y10S430/168
摘要： A photolithographic system includes individually controllable radiation sources for forming an image pattern on an image plane without using a reticle or mask during fabrication of an integrated circuit device. The radiation sources are selectively activated as they scan the image plane. The image pattern can consist of parallel lines having identical widths and varying lengths, or alternatively, pixels having identical shapes and sizes. The radiation sources can be arranged as a linear array, or a staggered array, to achieve the desired linear density. Suitable radiation sources include light pipes, light emitting diodes, and laser diodes. Preferably, each of the activated radiation sources provides an exposure field of less than 0.1 microns on the image plane, and at least two of the radiation sources must be activated to provide the minimum line width of the image pattern.
摘要翻译：光刻系统包括单独可控的辐射源，用于在集成电路器件的制造期间在图像平面上形成图像图案而不使用掩模版或掩模。当扫描图像平面时，辐射源被选择性地激活。图像图案可以由具有相同宽度和变化长度的平行线组成，或者替代地，具有相同形状和尺寸的像素。辐射源可以被布置为线性阵列或交错阵列，以实现期望的线密度。合适的辐射源包括光管，发光二极管和激光二极管。优选地，每个激活的辐射源在图像平面上提供小于0.1微米的曝光场，并且必须激活至少两个辐射源以提供图像图案的最小线宽。

78. 发明授权

US5801075A Method of forming trench transistor with metal spacers 失效
标题翻译：用金属间隔物形成沟槽晶体管的方法
公开(公告)号：US5801075A
公开(公告)日：1998-09-01
申请号：US739593
申请日：1996-10-30
申请人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Mark I. Gardner , Robert Dawson , H. Jim Fulford, Jr. , Frederick N. Hause , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/336 , H01L29/417 , H01L29/423 , H01L21/8238
CPC分类号： H01L29/41775 , H01L29/66621 , H01L29/78
摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
摘要翻译：公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体，覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

79. 发明授权

US5643825A Integrated circuit isolation process 失效
标题翻译：集成电路隔离过程
公开(公告)号：US5643825A
公开(公告)日：1997-07-01
申请号：US366053
申请日：1994-12-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/762
摘要： An improved process is provided for forming field dielectric in lieu of local oxidation process often referred to as the "LOCOS" process. The improved process utilizes blanket formation of first and second dielectrics across an entire semiconductor substrate. In a subsequent step, both first and second dielectrics are selectively removed in areas overlying active regions. The first and second dielectrics are formed using a combination of thermal growth and/or chemical deposition. The resulting field dielectric structure is relatively thin, yet demonstrates superior dielectric properties. Blanket formation followed by select removal ensures a fine-line demarcation between field and active regions and substantially eliminates encroachment problems normally associated with conventional LOCOS. Additionally, the thin field dielectric structure can be formed with rounded or reflowed corners to avoid step coverage problems for subsequently placed conductive elements.
摘要翻译：提供了用于形成场电介质以代替通常称为“LOCOS”工艺的局部氧化工艺的改进方法。改进的方法利用穿过整个半导体衬底的第一和第二电介质的覆盖层形成。在随后的步骤中，第一和第二电介质在覆盖有源区域的区域中被选择性地去除。使用热生长和/或化学沉积的组合形成第一和第二电介质。所得到的场介电结构相对较薄，但表现出优异的介电性能。毯子形成，然后选择移除确保场和活动区域之间的细线划分，并且基本上消除通常与常规LOCOS相关联的侵入问题。此外，薄场电介质结构可以形成为圆形或回流角，以避免随后放置的导电元件的步骤覆盖问题。

80. 发明授权

US5811347A Nitrogenated trench liner for improved shallow trench isolation 失效
标题翻译：氮化沟槽衬垫，用于改善浅沟槽隔离
公开(公告)号：US5811347A
公开(公告)日：1998-09-22
申请号：US641028
申请日：1996-04-29
申请人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
发明人： Mark I. Gardner , Fred N. Hause , Kuang-Yeh Chang
IPC分类号： H01L21/314 , H01L21/318 , H01L21/762 , H01L21/76
CPC分类号： H01L21/3144 , H01L21/3185 , H01L21/76224 , Y10S148/05
摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO.sub.2 trench liner and subsequently implanting the SiO.sub.2 trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.
摘要翻译：一种在半导体衬底内的有源区之间形成改进的隔离沟槽的方法。改进的方法包括氮含量为约0.5至2.0％的沟槽衬垫。在硅衬底上形成衬垫层，并在衬垫层上形成氮化物层。此后，在氮化硅层上图案化光致抗蚀剂层，使得随后将形成隔离沟槽的氮化物层的区域被暴露。接下来，蚀刻掉位于氮化物层的暴露区域之下的氮化物层和焊盘层的暴露区域以暴露硅衬底的区域。随后，用干蚀刻工艺将隔离沟槽蚀刻到硅衬底中。然后形成沟槽衬垫，并且氮结合到沟槽衬里中。通过在存在氮气环境的情况下形成沟槽衬垫或通过形成纯的SiO 2沟槽衬垫并随后用氮气注入SiO 2沟槽衬垫，可以将氮掺入到沟槽衬里中。在形成氮化沟槽衬垫之后，用优选由CVD氧化物构成的电介质填充沟槽。此后，CVD填充电介质被平坦化，并且氮化物层被剥离。

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