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71. 发明授权

US5748202A Image data processor for processing pixel data in block buffer 失效
标题翻译：用于处理块缓冲器中的像素数据的图像数据处理器
公开(公告)号：US5748202A
公开(公告)日：1998-05-05
申请号：US498055
申请日：1995-07-05
申请人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
发明人： Yasuhiro Nakatsuka , Keisuke Nakashima , Shigeru Matsuo , Masahisa Narita , Koyo Katsura , Hidehito Takewa , Tomoaki Aoki
IPC分类号： G06T3/00 , G06T1/20 , G06T15/40 , G06F12/00
CPC分类号： G06T15/40 , G06T1/20
摘要： In a device and system which perform processing, (displaying and outputting) of image data, the amount of data transferred between a memory holding the image data and a processor processing the image data is limited, thereby a great amount of data can be processed at high speed.
摘要翻译：在执行图像数据的处理（显示和输出）的装置和系统中，保持图像数据的存储器和处理图像数据的处理器之间传送的数据量受到限制，从而可以处理大量数据高速。

72. 发明授权

US5696540A Display controller 失效
标题翻译：显示控制器
公开(公告)号：US5696540A
公开(公告)日：1997-12-09
申请号：US799889
申请日：1991-12-02
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/14 , G09G5/32 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , G09G5/397 , G09G1/00
CPC分类号： G09G5/36 , G09G5/363 , G09G5/39 , G09G5/397
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译：在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性通过将单位时钟分割成预定数量以高速功能和多功能显示。当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示。所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。

73. 发明授权

US5657045A Graphic pattern processing apparatus 失效
标题翻译：图形处理装置
公开(公告)号：US5657045A
公开(公告)日：1997-08-12
申请号：US430851
申请日：1995-04-28
申请人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
发明人： Koyo Katsura , Hideo Maejima , Hisashi Kajiwara
IPC分类号： G06T1/20 , G06T1/60 , G06T11/20 , G06T17/00 , G09G5/02 , G09G5/20 , G09G5/36 , G09G5/39 , G09G5/393 , G09G5/395 , G09G5/399 , G09G5/38
CPC分类号： G09G5/395 , G06T1/20 , G06T1/60 , G06T11/203 , G06T17/00 , G09G5/024 , G09G5/20 , G09G5/363 , G09G5/39 , G09G5/393 , G09G5/399 , G09G2360/127 , G09G5/36
摘要： A graphic data generating apparatus includes a data processor, a graphic memory, and a graphic processor. The data processor outputs instructions to the graphic processor for processing graphic data. The instructions include a drawing instruction for transferring graphic data stored in a predetermined location in the graphic memory to another predetermined location in the graphic memory. The graphic memory stores pixel data defining the graphic data and each of the pixel data having a plurality of bits. The graphic processor performing read out of word data having a plurality of pixel data at a word position of the graphic memory specified by a source memory address, selecting pixel data specified by a source pixel address in the readout word and writing the selected pixel data in the graphic memory at a pixel position specified by a destination pixel address of word data specified by the destination memory address.
摘要翻译：图形数据生成装置包括数据处理器，图形存储器和图形处理器。数据处理器向图形处理器输出指令以处理图形数据。指令包括用于将存储在图形存储器中的预定位置的图形数据传送到图形存储器中的另一预定位置的绘图指令。图形存储器存储定义图形数据的像素数据，并且每个像素数据具有多个位。图形处理器执行读出由源存储器地址指定的图形存储器的字位置处的多个像素数据的字数据，选择由读出字中的源像素地址指定的像素数据，并将所选择的像素数据写入在由目的地存储器地址指定的字数据的目标像素地址指定的像素位置处的图形存储器。

74. 发明授权

US5373469A Differential amplifier with a latching function and a memory apparatus employing same 失效
标题翻译：具有锁存功能的差分放大器和采用该功能的存储装置
公开(公告)号：US5373469A
公开(公告)日：1994-12-13
申请号：US890260
申请日：1992-05-29
申请人： Takashi Akioka , Noboru Akiyama , Yutaka Kobayashi , Tatsuyuki Ohta , Koyo Katsura
发明人： Takashi Akioka , Noboru Akiyama , Yutaka Kobayashi , Tatsuyuki Ohta , Koyo Katsura
IPC分类号： G11C11/417 , G09G5/36 , G09G5/39 , G09G5/393 , G11C7/06 , G11C11/407 , G11C11/409 , G11C11/414 , H03K19/013 , H03K19/0944 , G11C7/00 , H03K19/086
CPC分类号： H03K19/09448 , G09G5/363 , G09G5/393 , G11C7/062 , G11C7/065 , H03K19/0136 , G09G2360/121
摘要： A high-speed memory employing the pipeline technique is disclosed, in which the minimum operating cycle time is reduced by use of a latch circuit for a small signal using a bipolar transistor. A small-signal latch circuit operating at a signal smaller than an output signal level is inserted between an amplifier circuit for amplifying the data held in a memory cell circuit and an output buffer circuit. A switch signal is also interposed between the latch circuit and the amplifier circuit, thereby shortening the cycle time.
摘要翻译：公开了一种采用流水线技术的高速存储器，其中通过使用双极晶体管的小信号的锁存电路来减小最小工作周期时间。操作在小于输出信号电平的信号的小信号锁存电路被插入放大器电路，用于放大存储单元电路中保存的数据和输出缓冲电路。开关信号也插入在锁存电路和放大器电路之间，从而缩短了周期时间。

75. 发明授权

US5202962A Graphic processor suitable for graphic data transfer and conversion processes 失效
标题翻译：图形处理器适用于图形数据传输和转换过程
公开(公告)号：US5202962A
公开(公告)日：1993-04-13
申请号：US544503
申请日：1990-06-27
申请人： Shigeru Matsuo , Koyo Katsura , Jun Sato , Takashi Sone , Masakatu Yokoyama
发明人： Shigeru Matsuo , Koyo Katsura , Jun Sato , Takashi Sone , Masakatu Yokoyama
IPC分类号： G06T17/00
CPC分类号： G06T17/00
摘要： A graphic processor which controls reading, writing and transfer of graphic data for a display memory that stores graphic data. The processor includes a first unit which stores first address information for addressing the display memory and first pixel address information which points a pixel position in a word specified by the first address information, a second unit which stores second address information for addressing the display memory and second pixel address information which points a pixel position in a word specified by the second address information, a third unit which shifts graphic data of multiple pixels included in two consecutive words to extract continuous 1-word graphic data, and a fourth unit which implements drawing computations pixel-wise concurrently for one word depending on the number of pixels included in a word. Even if transfer source graphic data lies across two consecutive words, the processor fetches the source data in single reading, processes the data word-wise at once, and stores the result in the display memory.
摘要翻译：用于控制用于存储图形数据的显示存储器的图形数据的读取，写入和传送的图形处理器。处理器包括第一单元，其存储用于寻址显示存储器的第一地址信息和指向由第一地址信息指定的字中的像素位置的第一像素地址信息;第二单元，存储用于寻址显示存储器的第二地址信息;以及指定由第二地址信息指定的字中的像素位置的第二像素地址信息;移动包括在两个连续字中的多个像素的图形数据以提取连续的1字图形数据的第三单元;以及实现绘图的第四单元根据包含在一个单词中的像素数量，对一个单词进行像素同步的计算。即使传输源图形数据位于两个连续的字中，处理器以单次读取的方式读取源数据，一次处理数据，并将结果存储在显示存储器中。

76. 发明授权

US5175811A Font data processor using addresses calculated on the basis of access parameters 失效
标题翻译：使用基于访问参数计算的地址的FONT数据处理器
公开(公告)号：US5175811A
公开(公告)日：1992-12-29
申请号：US804462
申请日：1991-12-05
申请人： Takashi Sone , Jun Sato , Koyo Katsura , Shigeru Matsuo
发明人： Takashi Sone , Jun Sato , Koyo Katsura , Shigeru Matsuo
IPC分类号： G09G5/24 , G06F3/14 , G06F15/62 , G09G5/22
CPC分类号： G09G5/24
摘要： A font processing system includes font pattern storage for defining a font pattern and font pattern access parameter storage for storing parameters for making access to the font pattern storage. Address calculation is made on the basis of the font pattern access parameter and a pattern code supplied from outside to indicate a font pattern. The font pattern processing system includes a pattern drawing attribute indicator for indicating the attributes of pattern drawing by the font pattern data thus read out. The present invention processes predetermined font data at a high speed inside a font data processor on the basis of the pattern code and can easily accomplish diversification of font patterns.
摘要翻译：字体处理系统包括用于定义字体图案的字体图案存储和用于存储用于访问字体图案存储的参数的字体图案访问参数存储。基于字体图案访问参数和从外部提供的图案代码来指示字体图案进行地址计算。字体图案处理系统包括用于通过读出的字体图案数据指示图案绘制的属性的图案绘图属性指示符。本发明基于图案代码在字体数据处理器内高速处理预定的字体数据，并且可以容易地实现字体图案的多样化。

77. 发明授权

US4720708A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US4720708A
公开(公告)日：1988-01-19
申请号：US686594
申请日：1984-12-26
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/00
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给其他CRTC的同步终端。用于控制其它CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

78. 发明授权

US4677549A Pipelined data processor system having increased processing speed 失效
标题翻译：流水线数据处理器系统具有提高的处理速度
公开(公告)号：US4677549A
公开(公告)日：1987-06-30
申请号：US469047
申请日：1983-02-23
申请人： Koyo Katsura , Hideo Maejima
发明人： Koyo Katsura , Hideo Maejima
IPC分类号： G06F9/38 , G06F9/22 , G06F9/28 , G06F13/00
CPC分类号： G06F9/3824 , G06F9/28
摘要： The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.
摘要翻译：本发明涉及一种基于流水线控制系统的数字数据处理器，当读取微程序所需的时间相对较短时，该处理器特别有效。微循环基于读取微程序所需的时间，并且通过根据确定的微循环将其分割在管道系统中来执行对数据的操作。这通过在算术单元的输出侧提供目的地锁存寄存器来完成。本发明还涉及其中目的地锁存寄存器被提供在运算单元的输入侧上，或者当目的地锁存寄存器被并入运算单元内的处理器，以及用于避免任何可能对寄存器进行争用的电路设置在执行当前指令时产生，并且根据添加的微程序提供下一指令。

79. 发明授权

US07333116B2 Data processor having unified memory architecture using register to optimize memory access 有权
标题翻译：具有使用寄存器的统一存储器架构的数据处理器来优化存储器访问
公开(公告)号：US07333116B2
公开(公告)日：2008-02-19
申请号：US11182944
申请日：2005-07-18
申请人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
发明人： Tetsuya Shimomura , Shigeru Matsuo , Koyo Katsura , Tatsuki Inuzuka , Yasuhiro Nakatsuka
IPC分类号： G09G5/39 , G09G5/36 , G06F13/14 , G06F15/167
CPC分类号： G09G5/001 , G06F13/1673 , G06F13/18 , G09G5/02 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2340/02 , G09G2360/121 , G09G2360/125 , G09G2360/128
摘要： In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.
摘要翻译：为了减少由于使用主存储器的一部分作为显示帧缓冲器而导致的数据处理器的处理性能的劣化，当从CPU 310产生对存储器200的访问请求时，存储器控制器400保持一旦请求显示控制器560停止对正在执行的存储器200的访问，当已经从存储器200传送已经执行的访问的数据时，显示控制器560保持它，并且从被保持的CPU总线310传送访问请求由存储器200。当CPU总线310的访问结束时，存储器控制器400重启在显示控制器560中停止的访问，并将保持的数据传送到显示控制器560。

80. 再颁专利

USRE39529E1 Graphic processing apparatus utilizing improved data transfer to reduce memory size 有权
标题翻译：利用改进的数据传输来减少存储器大小的图形处理装置
公开(公告)号：USRE39529E1
公开(公告)日：2007-03-27
申请号：US09536646
申请日：2000-03-28
申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
发明人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
IPC分类号： G09G5/39
CPC分类号： G09G5/393
摘要： A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.
摘要翻译：存储器接口和视频属性控制器（MIVAC）插入在能够进行连续数据读取操作的动态RAM（DRAM）之间，诸如与静态列模式，页面模式或半字节模式相关联的操作，以及图形处理器提供并行数据处理。在MIVAC和DRAM之间的每个数据总线上执行串行数据传输，而在MIVAC和图形处理器之间进行并行数据传输。结果，图形处理器可以被配置为具有减少数量的DRAM，使得图形处理器在不关注DRAM的连续数据读取模式的情况下操作。

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