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71. 发明授权

US07700993B2 CMOS EPROM and EEPROM devices and programmable CMOS inverters 有权
标题翻译： CMOS EPROM和EEPROM器件以及可编程CMOS反相器
公开(公告)号：US07700993B2
公开(公告)日：2010-04-20
申请号：US11935143
申请日：2007-11-05
申请人： Jin Cai , Tak H. Ning , John M. Safran
发明人： Jin Cai , Tak H. Ning , John M. Safran
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , G11C16/0433 , G11C16/10 , H01L21/823885 , H01L21/84 , H01L27/0922 , H01L27/105 , H01L27/11521 , H01L27/11524 , H01L27/11558 , H01L27/1203 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.
摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。厚栅极电介质层基本上比薄栅极电介质层厚。连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。

72. 发明申请

US20090302388A1 Method for Fabricating Super-Steep Retrograde Well Mosfet on SOI or Bulk Silicon Substrate, and Device Fabricated in Accordance with the Method 有权
标题翻译：在SOI或体硅衬底上制造超陡逆行阱Mosfet的方法，以及按照该方法制造的器件
公开(公告)号：US20090302388A1
公开(公告)日：2009-12-10
申请号：US12542879
申请日：2009-08-18
申请人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
发明人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

73. 发明申请

US20090134925A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20090134925A1
公开(公告)日：2009-05-28
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

74. 发明申请

US20090108350A1 Method For Fabricating Super-Steep Retrograde Well Mosfet On SOI or Bulk Silicon Substrate, And Device Fabricated In Accordance With The Method 有权
标题翻译：在SOI或体硅衬底上制造超陡逆向阱的方法以及根据该方法制造的器件
公开(公告)号：US20090108350A1
公开(公告)日：2009-04-30
申请号：US11925069
申请日：2007-10-26
申请人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
发明人： Jin Cai , Amlan Majumdar , Tak H. Ning , Zhibin Ren
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

75. 发明授权

US07323382B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权
标题翻译：内部去耦电容器，制造和测试电路的方法
公开(公告)号：US07323382B2
公开(公告)日：2008-01-29
申请号：US11707060
申请日：2007-02-16
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

76. 发明授权

US07195971B2 Method of manufacturing an intralevel decoupling capacitor 有权
标题翻译：制造级联去耦电容器的方法
公开(公告)号：US07195971B2
公开(公告)日：2007-03-27
申请号：US11066738
申请日：2005-02-28
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01L21/8242
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

77. 发明授权

US06677637B2 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same 有权
标题翻译：内部去耦电容器，制造和测试电路的方法
公开(公告)号：US06677637B2
公开(公告)日：2004-01-13
申请号：US09330803
申请日：1999-06-11
申请人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
发明人： Kerry Bernstein , John A. Bracchitta , William J. Cote , Tak H. Ning , Wilbur D. Pricer
IPC分类号： H01C2992
CPC分类号： H01G4/1272 , H01G4/35 , H01L22/14 , H01L22/22 , H01L23/5223 , H01L23/642 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , Y10T29/435 , H01L2924/00
摘要： A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.
摘要翻译：为半导体器件提供去耦电容器，并且可以包括在单个互连平面中在第一低介电绝缘体的表面上形成至少两个交叉指示图案的第一低介电绝缘体层和低电阻导体。可以在两个图案之间提供高介电常数材料。还提供了用于测试多个这些电容器的电路，其包括充电监视电路，耦合电路和控制电路。

78. 发明授权

US5581101A FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures 失效
标题翻译： FET和/或双极器件形成在薄的垂直绝缘体上硅（SOI）结构中
公开(公告)号：US5581101A
公开(公告)日：1996-12-03
申请号：US368069
申请日：1995-01-03
申请人： Tak H. Ning , Ben S. Wu
发明人： Tak H. Ning , Ben S. Wu
IPC分类号： H01L21/331 , H01L21/336 , H01L27/12 , H01L29/786 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66666 , H01L29/78642
摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.
摘要翻译：一种在绝缘体（SOI）技术中制造超大规模集成（ULSI）电路的工艺，其中可以是双极型，场效应晶体管或组合的器件结构形成在其下面和后面具有绝缘的垂直硅侧壁中以便创建SKI设备结构。当制造时，硅侧壁器件SOI结构采取单元的形式，每个单元具有多个双极器件，FET器件或这些器件的组合，例如集电极，发射极，基极，源极，漏极和栅极在单元中的器件的区域的平面内互连并且可以在相邻单元中的器件的区域的平面内互连。此外，可以从硅侧壁的背面形成与相邻单元的互连。

79. 发明授权

US5506457A Electronic switch for decoupling capacitor 失效
标题翻译：用于去耦电容的电子开关
公开(公告)号：US5506457A
公开(公告)日：1996-04-09
申请号：US418971
申请日：1995-04-07
申请人： Byron L. Krauter , Peter J. Klim , Tak H. Ning , Stanley E. Schuster , Lloyd A. Walls
发明人： Byron L. Krauter , Peter J. Klim , Tak H. Ning , Stanley E. Schuster , Lloyd A. Walls
IPC分类号： H01L27/08 , H03K17/22 , H01H83/20
CPC分类号： H01L27/0805 , H03K17/22 , Y10T307/852
摘要： An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.
摘要翻译：电子开关电路在高速集成电路芯片上切断不良去耦电容。该电路包括一个在亚阈值或者关断器件状态下操作以检测去耦电容器中的泄漏的控制装置。如果电容器良好，则该控制装置工作在低阻抗状态，如果电容器坏，则其工作在高阻抗状态。反馈电路从电容器的内部节点连接到控制装置的栅极，使得一旦电容器的状态被检测到，就可将其存储在控制装置的栅极上。由一组电容器共享的单个外部信号源激活控制装置以检测电容器中的泄漏。该电路用于切换在正常操作期间失败的电容器。

80. 发明授权

US4492008A Methods for making high performance lateral bipolar transistors 失效
标题翻译：制造高性能横向双极晶体管的方法
公开(公告)号：US4492008A
公开(公告)日：1985-01-08
申请号：US520366
申请日：1983-08-04
申请人： Narasipur G. Anantha , Tak H. Ning , Paul J. Tsang
发明人： Narasipur G. Anantha , Tak H. Ning , Paul J. Tsang
IPC分类号： H01L21/331 , H01L21/74 , H01L21/8222 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L29/73 , H01L29/732 , H01L29/735 , H01L27/08 , H01L21/76
CPC分类号： H01L29/6625 , H01L21/743 , H01L21/8224 , H01L27/0821 , H01L29/735
摘要： A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove. The P+ polycrystalline silicon layer is then formed on the surface which will in turn fill the groove with this material. The heating of the structure forms the P+ emitter region around the side edges of the P+ polycrystalline silicon filled groove. The P+ polycrystalline layer is the emitter contact, the N+ reach-through connected through the buried N+ region is the base contact and the collector contact is made to the P-type collector region.
摘要翻译：可以通过首先提供具有主表面的单晶半导体主体并且其中期望的晶体管是PNP晶体管，具有将掩埋区域连接到所述主表面的N +到达通孔的掩埋N +区域来制造高性能横向晶体管。晶体管的集电极区域通过将P型杂质铺展成期望的区域而形成为表面。绝缘层形成在半导体本体的顶表面上。在需要沟槽或沟道 - 发射极接触的绝缘层中形成开口。使用图案化绝缘层作为蚀刻掩模，将基本垂直的壁槽蚀刻到单晶半导体本体中。进行N基扩散以在体内的开口的周边周围产生N区。然后将氧离子注入凹槽的底部，以在凹槽的底部形成二氧化硅区域。然后在表面上形成P +多晶硅层，该表面依次用该材料填充凹槽。结构的加热在P +多晶硅填充槽的侧边缘周围形成P +发射极区域。 P +多晶层是发射极接触，通过埋入N +区连接的N +到达通孔是基极接触，并且集电极接触到P型集电极区域。

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