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1. 发明授权

US5581101A FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures 失效
标题翻译： FET和/或双极器件形成在薄的垂直绝缘体上硅（SOI）结构中
公开(公告)号：US5581101A
公开(公告)日：1996-12-03
申请号：US368069
申请日：1995-01-03
申请人： Tak H. Ning , Ben S. Wu
发明人： Tak H. Ning , Ben S. Wu
IPC分类号： H01L21/331 , H01L21/336 , H01L27/12 , H01L29/786 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66666 , H01L29/78642
摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.
摘要翻译：一种在绝缘体（SOI）技术中制造超大规模集成（ULSI）电路的工艺，其中可以是双极型，场效应晶体管或组合的器件结构形成在其下面和后面具有绝缘的垂直硅侧壁中以便创建SKI设备结构。当制造时，硅侧壁器件SOI结构采取单元的形式，每个单元具有多个双极器件，FET器件或这些器件的组合，例如集电极，发射极，基极，源极，漏极和栅极在单元中的器件的区域的平面内互连并且可以在相邻单元中的器件的区域的平面内互连。此外，可以从硅侧壁的背面形成与相邻单元的互连。

2. 发明授权

US08940548B2 Sensor for biomolecules 有权
标题翻译：生物分子传感器
公开(公告)号：US08940548B2
公开(公告)日：2015-01-27
申请号：US13552727
申请日：2012-07-19
申请人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
发明人： Marwan H. Khater , Tak H. Ning , Lidija Sekaric , Sufi Zafar
IPC分类号： G01N33/552 , G01N33/543 , B82Y10/00 , H01L29/78
CPC分类号： G01N33/54373 , B82Y10/00 , G01N27/3276 , G01N27/4145 , G01N33/543 , H01L29/785 , Y10S977/721 , Y10S977/92 , Y10S977/953
摘要： A method for sensing biomolecules in an electrolyte includes exposing a gate dielectric surface of a sensor comprising a silicon fin to the electrolyte, wherein the gate dielectric surface comprises a dielectric material and antibodies configured to bind with the biomolecules; applying a gate voltage to an electrode immersed in the electrolyte; and measuring a change in a drain current flowing in the silicon fin; and determining an amount of the biomolecules that are present in the electrolyte based on the change in the drain current.
摘要翻译：用于感测电解质中的生物分子的方法包括将包含硅翅片的传感器的栅极电介质表面暴露于电解质，其中所述栅极电介质表面包括电介质材料和被配置为与所述生物分子结合的抗体; 对浸在电解质中的电极施加栅极电压; 并测量在硅片中流动的漏极电流的变化; 以及基于漏极电流的变化确定存在于电解质中的生物分子的量。

3. 发明申请

US20140027871A1 CHARGE SENSORS USING INVERTED LATERAL BIPOLAR JUNCTION TRANSISTORS 有权
标题翻译：充电传感器使用反转的双极双极晶体管
公开(公告)号：US20140027871A1
公开(公告)日：2014-01-30
申请号：US13561671
申请日：2012-07-30
申请人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
发明人： Jin Cai , Tak H. Ning , Jeng-Bang Yau , Sufi Zafar
IPC分类号： H01L27/14
CPC分类号： G01T1/247 , G01N27/403 , G01T3/08 , H01L27/14 , H01L27/14681 , H01L31/022408 , H01L31/035272 , H01L31/1105 , H01L31/115 , H01L31/118
摘要： A sensor includes a collector, an emitter and a base-region barrier formed as an inverted bipolar junction transistor having a base substrate forming a base electrode to activate the inverted bipolar junction transistor. A level surface is formed by the collector, the emitter and the base-region barrier opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.
摘要翻译：传感器包括集电极，发射极和形成为反相双极结型晶体管的基极区势垒，其具有形成基极的基极以激活反相双极结型晶体管。由集电极，发射极和基极区域与基底基板相对的方式形成电平表面，使得当电平表面暴露于电荷时，在双极结晶体管的操作期间测量电荷。

4. 发明授权

US08586441B1 Germanium lateral bipolar junction transistor 有权
标题翻译：锗横向双极结晶体管
公开(公告)号：US08586441B1
公开(公告)日：2013-11-19
申请号：US13611606
申请日：2012-09-12
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Bahman Hekmatshoartabari , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/331
CPC分类号： H01L29/6625 , H01L29/161 , H01L29/735
摘要： A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.
摘要翻译：使用绝缘体上的锗（GOI）衬底形成锗横向双极结型晶体管（BJT）。在GOI衬底的锗层的顶表面上沉积硅钝化层。随后形成浅沟槽隔离结构，非本征基区结构和基底间隔物。通过离子注入在锗层内形成锗发射极区，锗基区和锗集电极区。在硅钝化层中形成硅发射极区域，硅基区域和硅集电极区域。在可选地形成发射极接触区域和集电极接触区域之后，可以形成金属半导体合金区域。在硅基区和锗基区之间以及硅发射极区和锗发射极区之间提供少量载流子的宽间隙接触。

5. 发明申请

US20130299906A1 BURIED-CHANNEL FIELD-EFFECT TRANSISTORS 有权
标题翻译： BURIED-CHANNEL场效应晶体管
公开(公告)号：US20130299906A1
公开(公告)日：2013-11-14
申请号：US13474949
申请日：2012-05-18
申请人： KANGGUO CHENG , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
发明人： KANGGUO CHENG , Ali Khakifirooz , Pranita Kulkarni , Tak H. Ning
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L29/0642 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0692 , H01L29/1054 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78 , H01L29/78687 , H01L29/78696
摘要： A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.
摘要翻译：掩埋沟道场效应晶体管包括形成在基板上的半导体层。半导体层包括掺杂的源极和漏极区域以及未掺杂的沟道区域。所述晶体管还包括形成在所述沟道区上并部分地与所述源极和漏极区重叠的栅极电介质; 形成在栅极电介质上的栅极; 以及在栅极电介质和半导体层之间的掺杂屏蔽层。

6. 发明授权

US08435845B2 Junction field effect transistor with an epitaxially grown gate structure 失效
标题翻译：具有外延生长栅极结构的结型场效应晶体管
公开(公告)号：US08435845B2
公开(公告)日：2013-05-07
申请号：US13080690
申请日：2011-04-06
申请人： Tak H. Ning , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
发明人： Tak H. Ning , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/337
CPC分类号： H01L29/812 , H01L21/84 , H01L21/845 , H01L27/098 , H01L27/1203 , H01L29/66545 , H01L29/66848 , H01L29/66893 , H01L29/785 , H01L29/808
摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。去除替代栅极结构以提供对半导体衬底的暴露部分的开口。功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

7. 发明授权

US08420493B2 SOI SiGe-base lateral bipolar junction transistor 有权
标题翻译： SOI SiGe基极横向双极结晶体管
公开(公告)号：US08420493B2
公开(公告)日：2013-04-16
申请号：US13556372
申请日：2012-07-24
申请人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
发明人： Tak H. Ning , Kevin K. Chan , Marwan H. Khater
IPC分类号： H01L21/331 , H01L21/336
CPC分类号： H01L29/7317 , H01L27/0821 , H01L27/1203 , H01L29/0808 , H01L29/165 , H01L29/66265
摘要： A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管（HBT）。 HBT包括基底，其包括掺杂的硅 - 锗合金基底区域，包括掺杂硅并且横向接触基底的发射体，以及包括掺杂硅并且横向接触基底的收集器。因为集电极电流被引导通过掺杂的硅 - 锗基区，所以与使用硅沟道的可比较的双极晶体管相比，HBT可以容纳更大的电流密度。基底还可以包括上硅基区和/或下硅基区。在这种情况下，集电极电流集中在掺杂的硅 - 锗基区域中，从而最小化引入到基极周边的载流子散射的噪声。此外，寄生电容被最小化，因为发射极 - 基极结面积与集电极 - 基极结面积相同。

8. 发明申请

US20130015912A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20130015912A1
公开(公告)日：2013-01-17
申请号：US13612036
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F3/02
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

9. 发明申请

US20120313216A1 COMPLEMENTARY BIPOLAR INVERTER 有权
标题翻译：补充双极反相器
公开(公告)号：US20120313216A1
公开(公告)日：2012-12-13
申请号：US13158419
申请日：2011-06-12
申请人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
发明人： Jin Cai , Robert H. Dennard , Wilfried E. Haensch , Tak H. Ning
IPC分类号： H01L27/082 , H01L21/8228
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

10. 发明申请

US20120299102A1 FET with FUSI Gate and Reduced Source/Drain Contact Resistance 有权
标题翻译：具有FUSI门的FET和降低的源极/漏极接触电阻
公开(公告)号：US20120299102A1
公开(公告)日：2012-11-29
申请号：US13569741
申请日：2012-08-08
申请人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhang Zhen
发明人： Christian Lavoie , Tak H. Ning , Qiqing Ouyang , Paul Solomon , Zhang Zhen
IPC分类号： H01L29/786
CPC分类号： H01L29/66575 , H01L21/265 , H01L21/28097 , H01L29/458 , H01L29/4908 , H01L29/4975 , H01L29/66507 , H01L29/66545 , H01L29/66772 , H01L29/78 , H01L29/7839
摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.
摘要翻译：场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

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