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71. 发明申请

US20100045380A1 LOW DROP VOLTAGE REGULATOR WITH INSTANT LOAD REGULATION AND METHOD 有权
标题翻译：具有稳定负载调节和方法的低电压稳压器
公开(公告)号：US20100045380A1
公开(公告)日：2010-02-25
申请号：US12610944
申请日：2009-11-02
申请人： Vadim V. Ivanov , Keith E. Kunz
发明人： Vadim V. Ivanov , Keith E. Kunz
IPC分类号： H03F3/45
CPC分类号： G05F1/575
摘要： An LDO regulator (10) produces an output voltage (Vout) by applying the output voltage to a feedback input (6) of a differential input stage (10A) and applying an output (3) of the differential input stage to a gate of a first follower transistor (MP4) having a source coupled to an input (8) of a class AB output stage (10C) which generates the output voltage. Demanded load current is supplied by the output voltage during a dip in its value to a gate of a second follower transistor (MP5) having a gate coupled to the output of the input stage to decrease current in a current mirror (MN5,6) having an output coupled to a current source (I1) and a gate of an amplifying transistor (MN7). This causes the current source to rapidly turn on the amplifying transistor to cause it to rapidly turn on a cascode transistor (MN3), causing it to turn on a pass transistor (MP3) of the output stage.
摘要翻译： LDO调节器（10）通过将输出电压施加到差分输入级（10A）的反馈输入（6）并且将差分输入级的输出（3）施加到一个门极，产生输出电压（Vout）第一跟随器晶体管（MP4）具有耦合到产生输出电压的AB类输出级（10C）的输入端（8）的源极。所需负载电流在其下降期间的输出电压被提供给具有耦合到输入级的输出端的栅极的第二跟随器晶体管（MP5）的栅极，以减少电流镜（MN5,6）中的电流，耦合到电流源（I1）和放大晶体管（MN7）的栅极的输出。这使得电流源快速地导通放大晶体管，使其迅速接通共源共栅晶体管（MN3），使其导通输出级的传输晶体管（MP3）。

72. 发明授权

US07466201B1 Class AB output stage and method for providing wide supply voltage range 有权
标题翻译： AB类输出级和提供宽电源电压范围的方法
公开(公告)号：US07466201B1
公开(公告)日：2008-12-16
申请号：US11804866
申请日：2007-05-21
申请人： Vadim V. Ivanov , Ralph G. Oberhuber
发明人： Vadim V. Ivanov , Ralph G. Oberhuber
IPC分类号： H03F3/18
CPC分类号： H03F3/45192 , H03F3/3022 , H03F2200/513 , H03F2203/30015 , H03F2203/45091 , H03F2203/45644 , H03F2203/45646 , H03F2203/45648
摘要： A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.
摘要翻译： AB类输出级包括第一（MP）和第二（MN）输出晶体管，其具有耦合到第一（VDD）和第二参考电压的源，耦合到输出（13）的漏极，以及耦合到第一（11A）和第二（12A）导体。第一（IIN1）和第二（IIN2）输入电流的部分分别经由第一输入导体（11）和第二输入导体（12）来源于第一（M2）和第二（M4）晶体管的源极，分别。第一（M2）和第二（M4）晶体管的栅极分别耦合到第一和第二导体。第一（VrefP）和第二（VrefN）偏置电压分别施加到第三（M1）和第四（M3）晶体管的栅极，分别具有耦合到第一和第二输入导体的源极以及耦合到第二导体的漏极。

73. 发明申请

US20080174367A1 TAIL-CURRENT STEERING CIRCUIT AND METHOD FOR RAIL-TO-RAIL OPERATIONAL AMPLIFIER INPUT STAGE 有权
标题翻译：轨道电流转向电路和轨至轨运行放大器输入级的方法
公开(公告)号：US20080174367A1
公开(公告)日：2008-07-24
申请号：US11655524
申请日：2007-01-19
申请人： Vadim V. Ivanov , David R. W. Spady
发明人： Vadim V. Ivanov , David R. W. Spady
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F3/4565 , H03F2200/456 , H03F2203/45466 , H03F2203/45476
摘要： An amplifier includes first and second pairs of differentially coupled input transistors. The first current mirror generates a reference current which is mirrored by a second current mirror to produce a mirrored reference current. Current steering circuitry steers the mirrored reference current as a first tail current through the first pair when a common mode voltage associated with a differential input voltage exceeds a first reference voltage. A first portion of the mirrored reference current flows from the first current steering circuitry when the common mode voltage is greater than the first reference voltage to produce a second tail current for the second pair. A second portion of the mirrored reference current is fed back to an output of the first current mirror and summed with the reference current so as to reduce the second portion when the common mode voltage is greater than the first reference voltage.
摘要翻译：放大器包括第一对和第二对差分耦合输入晶体管。第一个当前镜像产生参考电流，该参考电流由第二个电流镜反射以产生镜像参考电流。当与差分输入电压相关联的共模电压超过第一参考电压时，电流转向电路将经镜像参考电流引导为通过第一对的第一尾电流。当共模电压大于第一参考电压时，镜像参考电流的第一部分从第一电流控制电路流动，以产生第二对的第二尾电流。镜像参考电流的第二部分被反馈到第一电流镜的输出并与参考电流相加，以便当共模电压大于第一参考电压时减小第二部分。

74. 发明授权

US06927624B2 Method and circuit for improving control of trimming procedure 有权
标题翻译：改善修剪程序控制的方法和电路
公开(公告)号：US06927624B2
公开(公告)日：2005-08-09
申请号：US10461117
申请日：2003-06-12
申请人： Vadim V. Ivanov , Stephen J. Sanchez , David M. Jones , David Spady
发明人： Vadim V. Ivanov , Stephen J. Sanchez , David M. Jones , David Spady
IPC分类号： H03F1/30 , G01R19/00
CPC分类号： H03F1/30 , H03F2200/261
摘要： A method and circuit is provided for improving the control of the trimming procedure for various devices without the need for additional dedicated control pins. Instead, the trimming procedure is controlled through sensing of changes in current and/or voltage applied through the existing available pins or bondpads of the devices to determine whether a command for trim programming has occurred. As a result, package-level trimming of the devices can be conducted in standard device packages having low pin count configurations, such as operational amplifiers, instrumentation amplifiers, difference amplifiers, low drop-out regulators, voltage references and other similar types of devices. A device to be trimmed is configured with internal circuitry configured to sense changes in current and/or voltage in the output or supply voltage of the device, and a test system for applying changes in the current and/or voltage through the existing available pins or bondpads of the devices. The internal circuitry can comprise sensing circuitry comprising one or more internal sensors configured to measure current and/or voltage in the output or supply voltage of the device, and can comprise trim programming circuitry for facilitating trim programming of the device.
摘要翻译：提供了一种方法和电路，用于改进对各种装置的修整程序的控制，而不需要额外的专用控制引脚。相反，通过感测通过设备的现有可用引脚或粘合垫施加的电流和/或电压的变化来控制修整过程，以确定是否发生了用于修剪编程的命令。因此，器件的封装级修整可以在具有低引脚数配置的标准器件封装中进行，例如运算放大器，仪表放大器，差分放大器，低压差稳压器，电压基准和其他类似类型的器件。被修整的装置被配置有内部电路，其被配置为感测装置的输出或电源电压中的电流和/或电压的变化，以及用于通过现有可用的引脚施加电流和/或电压的变化的测试系统，设备的bondpads。内部电路可以包括感测电路，其包括配置成测量设备的输出或电源电压中的电流和/或电压的一个或多个内部传感器，并且可以包括用于促进设备的微调编程的微调编程电路。

75. 发明授权

US06924672B2 CMOS comparator output stage and method 有权
标题翻译： CMOS比较器输出级和方法
公开(公告)号：US06924672B2
公开(公告)日：2005-08-02
申请号：US10694517
申请日：2003-10-27
申请人： Vadim V. Ivanov , Shoubao Yan , Walter B. Meinel
发明人： Vadim V. Ivanov , Shoubao Yan , Walter B. Meinel
IPC分类号： H03K17/00 , H03K17/0812 , H03K19/00 , H03K5/52
CPC分类号： H03K17/08122 , H03K19/0013 , H03K2217/0036
摘要： A CMOS circuit including a P-channel pull-up transistor (MP) and an N-channel pull-down transistor (MN) includes a first feedback circuit (6) producing a first delayed signal (V7) on the gate of the pull-down transistor (MN) to turn on the pull-down transistor (MN) a first predetermined amount of time after the pull-up transistor (MP) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN) and a second feedback circuit (4) producing a second delayed signal (V5) on the gate of the pull-up transistor (MP) to turn on the pull-up transistor (MP) a second predetermined amount of time after the pull-down transistor (MN) is turned completely off so as to prevent any shoot-through current from flowing through the pull-up transistor (MP) and the pull-down transistor (MN).
摘要翻译：包括P沟道上拉晶体管（MP）和N沟道下拉晶体管（MN）的CMOS电路包括产生第一延迟信号（V SUB）的第一反馈电路（6））在下拉晶体管（MN）的栅极上，以在上拉晶体管（MP）完全关断之后的第一预定量的时间导通下拉晶体管（MN），以防止任何拍摄 - 通过上拉电流流过上拉晶体管（MP）和下拉晶体管（MN）;以及第二反馈电路（4），其在栅极上产生第二延迟信号（V SUB 5）在下拉晶体管（MN）完全关闭之后，上拉晶体管（MP）接通上拉晶体管（MP）第二预定量的时间，以防止任何直通电流流过上拉晶体管（MP）和下拉晶体管（MN）。

76. 发明授权

US06807040B2 Over-current protection circuit and method 有权
标题翻译：过流保护电路及方法
公开(公告)号：US06807040B2
公开(公告)日：2004-10-19
申请号：US09839981
申请日：2001-04-19
申请人： Vadim V. Ivanov , David R. Baum
发明人： Vadim V. Ivanov , David R. Baum
IPC分类号： H02H908
CPC分类号： H03K17/0822 , H03F1/523
摘要： Over-current protection is accomplished in an output transistor (MP) of an electronic circuit wherein an input signal (Vgatedrive) Is Applying to a first conductor (19) coupled to a gate of the output transistor to cause an output current (Iout) to flow through the output transistor and an output terminal (11) of the electronic circuit. A limit voltage (VLIMIT) who is applied to an input (21) of a voltage clamping circuit (18) to cause a clamping current to flow in the first conductor (19) as needed to prevent the magnitude of the input signal (Vgatedrive) from being less than the magnitude of the limit voltage (VLIMIT) so that the output current (Iout) is limited to a maximum current limit determined by the limit voltage (VLIMIT). A control signal (ILIMIT/n) is applied to an input of a current-to-voltage conversion circuit (20) to cause the current-to-voltage conversion circuit to produce the limit voltage (VLIMIT), which is applied to an emitter of a first transistor (Q1) having a collector in base connected to a bias current source (I1). The resulting voltage on a base of the first transistor is applied to a base of a second transistor (Q2), and the input signal (Vgatedrive) is applied to the first conductor (19).
摘要翻译：过电流保护在电子电路的输出晶体管（MP）中完成，其中输入信号（Vgatedrive）施加到耦合到输出晶体管的栅极的第一导体（19），以使输出电流（Iout）流过输出晶体管和电子电路的输出端子（11）。施加到电压钳位电路（18）的输入（21）的限制电压（VLIMIT），以根据需要使钳位电流流过第一导体（19），以防止输入信号（Vgatedrive）的幅度，从小于限制电压（VLIMIT）的幅度，使得输出电流（Iout）被限制为由极限电压（VLIMIT）确定的最大电流限制。控制信号（ILIMIT / n）被施加到电流 - 电压转换电路（20）的输入，以使得电流 - 电压转换电路产生施加到发射极的极限电压（VLIMIT）具有与偏置电流源（I1）连接的基极集电极的第一晶体管（Q1）。将第一晶体管的基极上产生的电压施加到第二晶体管（Q2）的基极，并将输入信号（Vgatedrive）施加到第一导体（19）。

77. 发明授权

US06703900B2 Fast, stable overload recovery circuit and method 有权
标题翻译：快速，稳定的过载恢复电路及方法
公开(公告)号：US06703900B2
公开(公告)日：2004-03-09
申请号：US10163113
申请日：2002-06-05
申请人： Vadim V. Ivanov , Shilong Zhang , Gregory H. Johnson
发明人： Vadim V. Ivanov , Shilong Zhang , Gregory H. Johnson
IPC分类号： H03F152
CPC分类号： H03F3/3028 , H03F1/308 , H03F1/3217
摘要： A differential amplifier includes an input stage (13) and an output stage (100) including an output transistor (M11) having a source coupled to a supply voltage (VDD), a gate coupled to a terminal (14) of the input stage, and a drain coupled to an output conductor (22). A recovery circuit (1A) is coupled between the supply voltage and the gate of the output transistor for limiting the voltage on the gate of the output transistor in response to the output voltage be within a predetermined range of the supply voltage and includes a recovery transistor (M4) with a source coupled to the output conductor and a drain coupled to the gate of the output transistor and a common-gate amplifier (29A) having a built-in offset a first input coupled to the output conductor, a second input coupled to the supply voltage, and an output coupled to the gate of the recovery transistor.
摘要翻译：差分放大器包括输入级（13）和输出级（100），输出级（100）包括具有耦合到电源电压（VDD）的源极的输出晶体管（M11），耦合到输入级的端子（14）的栅极，以及耦合到输出导体（22）的漏极。恢复电路（1A）耦合在电源电压和输出晶体管的栅极之间，用于响应于输出电压在电源电压的预定范围内来限制输出晶体管的栅极上的电压，并且包括恢复晶体管（M4），其源极耦合到所述输出导体，以及耦合到所述输出晶体管的栅极的漏极和具有内置偏移的共栅极放大器（29A），所述第一输入耦合到所述输出导体，第二输入耦合并且耦合到恢复晶体管的栅极的输出。

78. 发明授权

US06700522B2 Signal settling device and method 有权
标题翻译：信号稳定装置及方法
公开(公告)号：US06700522B2
公开(公告)日：2004-03-02
申请号：US10154165
申请日：2002-05-23
申请人： Vadim V. Ivanov , Kevin Huckins
发明人： Vadim V. Ivanov , Kevin Huckins
IPC分类号： H03M112
CPC分类号： H03F3/45372 , H03F3/3028 , H03F3/45192 , H03F3/45269 , H03F3/45273 , H03F3/45291 , H03F3/45367 , H03F2200/331 , H03F2203/30084 , H03F2203/30096 , H03F2203/30117 , H03F2203/30129 , H03F2203/30151 , H03F2203/30156 , H03K17/04106
摘要： A method and device are configured for providing for both quick and accurate signal settling. A high accuracy component is configured in parallel with a high speed component. The high accuracy component may be an op-amp. The high speed component may be an OTA that is configured to be a non-linear OTA. Furthermore, an ADC is configured to internally provide both quick and accurate signal settling. For example, an ADC comprises an internal high speed OTA configured in parallel with a connected external op-amp. The OTA is configured to be a non-linear OTA.
摘要翻译：一种方法和装置被配置为提供快速和准确的信号稳定。高精度部件与高速部件并联配置。高精度分量可以是运算放大器。高速分量可以是被配置为非线性OTA的OTA。此外，ADC配置为内部提供快速和准确的信号稳定。例如，ADC包括与连接的外部运算放大器并联配置的内部高速OTA。 OTA配置为非线性OTA。

79. 发明授权

US06642789B2 Operational amplifier input stage and method 有权
标题翻译：运算放大器输入级和方法
公开(公告)号：US06642789B2
公开(公告)日：2003-11-04
申请号：US10094540
申请日：2002-03-08
申请人： Vadim V. Ivanov , Wally Meinel , Junlin Zhou
发明人： Vadim V. Ivanov , Wally Meinel , Junlin Zhou
IPC分类号： H03F345
CPC分类号： H03F3/4521 , H03F3/3028 , H03F3/45659 , H03F3/45677
摘要： A precision operational amplifier operating in single supply mode, including a single differential transistor input pair and a cascoded CMOS transistor pair, stabilizes the drain-to-source voltage of the input transistor pair to ensure a stable off-set voltage and increased power supply and common mode rejection. The precision amplifier biases the cascoded CMOS transistor pair in accordance with the stabilized drain-to-source voltage of the differential transistor input pair. Such biasing may take the form of body biasing or biasing the gates of the cascode CMOS transistor pair to ensure that the CMOS transistor pair remain in the active region of operation when the common mode supply voltage approaches zero.
摘要翻译：在单电源模式下工作的精密运算放大器，包括单个差分晶体管输入对和级联CMOS晶体管对，稳定输入晶体管对的漏极 - 源极电压，以确保稳定的偏置电压和增加的电源，共模拒绝精密放大器根据差分晶体管输入对的稳定的漏极 - 源极电压偏置级联CMOS晶体管对。这种偏置可以采取体的偏置或偏置共栅二极管CMOS晶体管对的栅极的形式，以确保当共模电源电压接近零时，CMOS晶体管对保持在有源工作区。

80. 发明授权

US06359512B1 Slew rate boost circuitry and method 有权
标题翻译：压摆率升压电路和方法
公开(公告)号：US06359512B1
公开(公告)日：2002-03-19
申请号：US09765267
申请日：2001-01-18
申请人： Vadim V. Ivanov , Shilong Zhang , Gregory H. Johnson
发明人： Vadim V. Ivanov , Shilong Zhang , Gregory H. Johnson
IPC分类号： H03F345
CPC分类号： H03F3/45183 , H03F1/3223 , H03F1/483 , H03F3/303 , H03F3/45192 , H03F2203/45682 , H03F2203/45702
摘要： An operational amplifier includes a differential input stage (30) having first (2) and second (3) input conductors, a class AB output stage (20) coupled to an output of the differential input stage (30) and including a pull-up transistor (M11) having a source coupled to a first supply voltage (VDD), a drain coupled to an output conductor (17), and a gate coupled to a first terminal (14) of a class AB control circuit (11), and a pull-down transistor (M12) having a source coupled to a second supply voltage (GND), a drain coupled to the output conductor (17), and a gate coupled to a second terminal (15) of the class AB control circuit (11). A differential input signal is applied between the first (2) and second (3) input conductors, and simultaneously also is applied between first and second inputs of a first unbalanced differential amplifier (31) and between first and second input to the second unbalanced differential amplifier (32). If the differential input signal is of a first polarity and is of a magnitude substantially greater than a threshold voltage of the first unbalanced differential amplifier (31), the magnitude of a turn-on voltage of the pull-down transistor (M12) is decreased and the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased in response to an output voltage produced by the first unbalanced differential amplifier (31). However, if the differential input signal is of a second polarity and is of a magnitude substantially greater than a threshold voltage of the second unbalanced differential amplifier (32), then the magnitude of a turn-on voltage of the pull-up transistor (M11) is increased and the magnitude of a turn-on voltage of the pull-down transistor (M12) is simultaneously decreased, in response to an output voltage produced by the second unbalanced differential amplifier (32).
摘要翻译：运算放大器包括具有第一（2）和第二（3）输入导体的差分输入级（30），耦合到差分输入级（30）的输出的AB类输出级（20）并且包括上拉晶体管（M11）具有耦合到第一电源电压（VDD）的源极，耦合到输出导体（17）的漏极和耦合到AB类控制电路（11）的第一端子（14）的栅极，以及具有耦合到第二电源电压（GND）的源极的下拉晶体管（M12），耦合到输出导体（17）的漏极和耦合到AB类控制电路的第二端子（15）的栅极 11）。差分输入信号施加在第一（2）和第二（3）输入导体之间，同时也被施加在第一不平衡差分放大器（31）的第一和第二输入端之间以及在第二和第二输入端之间的第二和第二输入端放大器（32）。如果差分输入信号具有第一极性并且具有显着大于第一不平衡差分放大器（31）的阈值电压的幅度，则下拉晶体管（M12）的接通电压的幅度减小并且上拉晶体管（M11）的接通电压的大小响应于由第一不平衡差分放大器（31）产生的输出电压而增加。然而，如果差分输入信号具有第二极性并且具有显着大于第二不平衡差分放大器（32）的阈值电压的幅度，则上拉晶体管（M11）的接通电压的幅度）并且响应于由第二不平衡差分放大器（32）产生的输出电压同时降低下拉晶体管（M12）的接通电压的幅度。

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