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1. 发明授权

US07466201B1 Class AB output stage and method for providing wide supply voltage range 有权
标题翻译： AB类输出级和提供宽电源电压范围的方法
公开(公告)号：US07466201B1
公开(公告)日：2008-12-16
申请号：US11804866
申请日：2007-05-21
申请人： Vadim V. Ivanov , Ralph G. Oberhuber
发明人： Vadim V. Ivanov , Ralph G. Oberhuber
IPC分类号： H03F3/18
CPC分类号： H03F3/45192 , H03F3/3022 , H03F2200/513 , H03F2203/30015 , H03F2203/45091 , H03F2203/45644 , H03F2203/45646 , H03F2203/45648
摘要： A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.
摘要翻译： AB类输出级包括第一（MP）和第二（MN）输出晶体管，其具有耦合到第一（VDD）和第二参考电压的源，耦合到输出（13）的漏极，以及耦合到第一（11A）和第二（12A）导体。第一（IIN1）和第二（IIN2）输入电流的部分分别经由第一输入导体（11）和第二输入导体（12）来源于第一（M2）和第二（M4）晶体管的源极，分别。第一（M2）和第二（M4）晶体管的栅极分别耦合到第一和第二导体。第一（VrefP）和第二（VrefN）偏置电压分别施加到第三（M1）和第四（M3）晶体管的栅极，分别具有耦合到第一和第二输入导体的源极以及耦合到第二导体的漏极。

2. 发明申请

US20080290945A1 CLASS AB OUTPUT STAGE AND METHOD FOR PROVIDING WIDE SUPPLY VOLTAGE RANGE 有权
标题翻译： AB类输出级和提供宽电源电压范围的方法
公开(公告)号：US20080290945A1
公开(公告)日：2008-11-27
申请号：US11804866
申请日：2007-05-21
申请人： Vadim V. Ivanov , Ralph G. Oberhuber
发明人： Vadim V. Ivanov , Ralph G. Oberhuber
IPC分类号： H03F3/18
CPC分类号： H03F3/45192 , H03F3/3022 , H03F2200/513 , H03F2203/30015 , H03F2203/45091 , H03F2203/45644 , H03F2203/45646 , H03F2203/45648
摘要： A class AB output stage includes first (MP) and a second (MN) output transistors having sources coupled to first (VDD) and second reference voltages, respectively, drains coupled to an output (13), and gates coupled to first (11A) and second (12A) conductors, respectively. Portions of first (IIN1) and a second (IIN2) input currents are sourced via a first input conductor (11) and a second input conductor (12), respectively, into and from sources of first (M2) and second (M4) transistors, respectively. Gates of the first (M2) and second (M4) transistors are coupled to the first and second conductors, respectively. First (VrefP) and second (VrefN) bias voltages are applied to gates of third (M1) and fourth (M3) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.
摘要翻译： AB类输出级包括第一（MP）和第二（MN）输出晶体管，其具有耦合到第一（VDD）和第二参考电压的源，耦合到输出（13）的漏极，以及耦合到第一（11A）和第二（12A）导体。第一（IIN1）和第二（IIN2）输入电流的部分分别经由第一输入导体（11）和第二输入导体（12）来源于第一（M2）和第二（M4）晶体管的源极，分别。第一（M2）和第二（M4）晶体管的栅极分别耦合到第一和第二导体。第一（VrefP）和第二（VrefN）偏置电压分别施加到第三（M1）和第四（M3）晶体管的栅极，分别具有耦合到第一和第二输入导体的源极以及耦合到第二导体的漏极。

3. 发明授权

US08514120B2 Digital-to-analog converter with a shared resistor string 有权
标题翻译：具有共享电阻串的数模转换器
公开(公告)号：US08514120B2
公开(公告)日：2013-08-20
申请号：US13291853
申请日：2011-11-08
申请人： Ralph G. Oberhuber , Tsedeniya A. Abraham , Mark Shill
发明人： Ralph G. Oberhuber , Tsedeniya A. Abraham , Mark Shill
IPC分类号： H03M1/66
CPC分类号： H03M1/0651 , H03M1/685
摘要： An apparatus is provided that comprises resistors, a first set of switches, and a second set of switches. The resistors are arranged in an array having columns and rows, where the number of resistors is an integer multiple of the number of columns or rows. The resistors are coupled together in a skip-K pattern. Each switch from the first and second sets of switches is coupled to the resistor string, and the first and second sets of switches are each arranged in a sequence and are offset from one another by an offset value. The first and second sets of switches are arranged along the periphery of the array such that each switch from the first set of switches is located in proximity to and is associated with the same row or the same column as its corresponding switch in the sequence from the second set of switches.
摘要翻译：提供一种装置，其包括电阻器，第一组开关和第二组开关。电阻器被布置成具有列和行的阵列，其中电阻器的数量是列或行的整数倍。电阻器以跳过K图案耦合在一起。来自第一和第二组开关的每个开关耦合到电阻器串，并且第一组开关和第二组开关各自以一个顺序排列并且彼此偏移一个偏移值。第一组和第二组开关沿着阵列的周边布置，使得来自第一组开关的每个开关位于与其对应的开关相同的行或相同的列上，其顺序与第二套开关。

4. 发明授权

US07796060B2 Circuits and methods to minimize nonlinearity errors in interpolating circuits 有权
标题翻译：最小化内插电路中的非线性误差的电路和方法
公开(公告)号：US07796060B2
公开(公告)日：2010-09-14
申请号：US12188014
申请日：2008-08-07
申请人： Ralph G. Oberhuber , Timothy V. Kalthoff
发明人： Ralph G. Oberhuber , Timothy V. Kalthoff
IPC分类号： H03M13/00
CPC分类号： H03M1/06 , H03M1/0682 , H03M1/682 , H03M1/747 , H03M1/765
摘要： Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.
摘要翻译：这里描述了最小化内插电路中的非线性误差的电路和方法。公开的示例电路包括第一和第二电压 - 电流转换器电路，每个电压 - 电流转换器电路各自包括第一晶体管和第二晶体管，每个具有第一电极，第一电极被配置为接收由相应的电流源产生的信号;第一电流源，第一电压转换器电路，并且包括第一误差校正电路，以通过设置通过第一电流源的第一电流来最小化内插电路中的积分非线性误差，以在标称线性运行模式下操作第一电压转换器电路，以及第二电流源向第二电压转换器电路提供信号，并且包括第二误差校正电路，以通过设置通过第二电流源的第二电流来最小化内插电路中的积分非线性误差，以在额定线性运行中操作第二电压转换器电路模式。

5. 发明申请

US20130113643A1 DIGITAL-TO-ANALOG CONVERTER WITH A SHARED RESISTOR STRING 有权
标题翻译：具有共享电阻器的数字模拟转换器
公开(公告)号：US20130113643A1
公开(公告)日：2013-05-09
申请号：US13291853
申请日：2011-11-08
申请人： Ralph G. Oberhuber , Tsedeniya A. Abraham , Mark Shill
发明人： Ralph G. Oberhuber , Tsedeniya A. Abraham , Mark Shill
IPC分类号： H03M1/66
CPC分类号： H03M1/0651 , H03M1/685
摘要： An apparatus is provided that comprises resistors, a first set of switches, and a second set of switches. The resistors are arranged in an array having columns and rows, where the number of resistors is an integer multiple of the number of columns or rows. The resistors are coupled together in a skip-K pattern. Each switch from the first and second sets of switches is coupled to the resistor string, and the first and second sets of switches are each arranged in a sequence and are offset from one another by an offset value. The first and second sets of switches are arranged along the periphery of the array such that each switch from the first set of switches is located in proximity to and is associated with the same row or the same column as its corresponding switch in the sequence from the second set of switches.
摘要翻译：提供一种装置，其包括电阻器，第一组开关和第二组开关。电阻器被布置成具有列和行的阵列，其中电阻器的数量是列或行的整数倍。电阻器以跳过K图案耦合在一起。来自第一和第二组开关的每个开关耦合到电阻器串，并且第一组开关和第二组开关各自以一个顺序排列并且彼此偏移一个偏移值。第一组和第二组开关沿着阵列的周边布置，使得来自第一组开关的每个开关位于与其对应的开关相同的行或相同的列上，其顺序与第二套开关。

6. 发明申请

US20100033356A1 CIRCUITS AND METHODS TO MINIMIZE NONLINEARITY ERRORS IN INTERPOLATING CIRCUITS 有权
标题翻译：最小化插入电路中非线性误差的电路和方法
公开(公告)号：US20100033356A1
公开(公告)日：2010-02-11
申请号：US12188014
申请日：2008-08-07
申请人： Ralph G. Oberhuber , Timothy V. Kalthoff
发明人： Ralph G. Oberhuber , Timothy V. Kalthoff
IPC分类号： H03M13/00
CPC分类号： H03M1/06 , H03M1/0682 , H03M1/682 , H03M1/747 , H03M1/765
摘要： Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.
摘要翻译：这里描述了最小化内插电路中的非线性误差的电路和方法。公开的示例电路包括第一和第二电压 - 电流转换器电路，每个电压 - 电流转换器电路各自包括第一晶体管和第二晶体管，每个具有第一电极，第一电极被配置为接收由相应的电流源产生的信号;第一电流源，第一电压转换器电路，并且包括第一误差校正电路，以通过设置通过第一电流源的第一电流来最小化内插电路中的积分非线性误差，以在标称线性运行模式下操作第一电压转换器电路，以及第二电流源向第二电压转换器电路提供信号，并且包括第二误差校正电路，以通过设置通过第二电流源的第二电流来最小化内插电路中的积分非线性误差，以在额定线性运行中操作第二电压转换器电路模式。

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