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71. 发明申请

US20060007729A1 Phase change memories and/or methods of programming phase change memories using sequential reset control 有权
标题翻译：相变存储器和/或使用顺序复位控制编程相变存储器的方法
公开(公告)号：US20060007729A1
公开(公告)日：2006-01-12
申请号：US11074557
申请日：2005-03-08
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.
摘要翻译：提供了包括多个相变存储器单元的相变存储器件和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多条复位线中相应的一条。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。还提供了使用顺序复位控制信号编程相变存储器件的方法。

72. 发明授权

US5936875A Integrated circuit memory devices including overlapping power lines and bit lines 失效
标题翻译：集成电路存储器件包括重叠的电源线和位线
公开(公告)号：US5936875A
公开(公告)日：1999-08-10
申请号：US979573
申请日：1997-11-26
申请人： Dae-Yong Kim , Du-Eung Kim , Young-Ho Suh , Choung-Keun Kwak
发明人： Dae-Yong Kim , Du-Eung Kim , Young-Ho Suh , Choung-Keun Kwak
IPC分类号： G11C11/41 , G11C5/06 , H01L21/8244 , H01L27/10 , H01L27/11 , G11C5/02
CPC分类号： G11C5/063
摘要： Integrated circuit memory devices include overlapping bit lines and power supply lines. The integrated circuit memory devices include a memory cell array in an integrated circuit substrate and a plurality of spaced apart bit lines on the memory cell array, extending in a first direction. A plurality of spaced apart power lines are also included on the memory cell array, extending in the first direction, and on at least one of the plurality of bit lines. The overlapping bit lines and power supply lines are insulated from one another, for example by providing these lines in first and second patterned conductive layers. Accordingly, higher density integrated circuit devices may be provided while allowing high speed operation and effective power supply voltage distribution.
摘要翻译：集成电路存储器件包括重叠位线和电源线。集成电路存储器件包括在集成电路衬底中的存储单元阵列和在第一方向上延伸的存储单元阵列上的多个间隔开的位线。多个间隔开的电源线还包括在存储单元阵列中，沿第一方向延伸，并且在多个位线中的至少一个位线上。重叠的位线和电源线彼此绝缘，例如通过在第一和第二图案化导电层中提供这些线。因此，可以提供更高密度的集成电路器件，同时允许高速操作和有效的电源电压分配。

73. 发明授权

US5487050A Decoding circuit and method for a semiconductor memory device 失效
标题翻译：半导体存储器件的解码电路和方法
公开(公告)号：US5487050A
公开(公告)日：1996-01-23
申请号：US229082
申请日：1994-04-18
申请人： Kyeong-Rae Kim , Seung-Kweon Yang , Hee-Choul Park , Du-Eung Kim
发明人： Kyeong-Rae Kim , Seung-Kweon Yang , Hee-Choul Park , Du-Eung Kim
IPC分类号： G11C11/41 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/12
摘要： A decoding circuit and method for a semiconductor memory device simplifies a decoding process by individually performing a large block decoding and small block decoding operations, and thereby reduces the total time delay taken in an address decoding process and layout area occupied by decoding circuits. The decoding circuit for a semiconductor memory device having a memory cell array including a plurality of large blocks, each large block including m small blocks (wherein m=2,3, . . . ) and having a plurality of memory cells being arranged in a matrix form, and a plurality of reading/writing circuits each corresponding to said large blocks, includes a first decoding circuit for receiving a first address to simultaneously select respective specific small block in each of the large blocks, corresponding to the first address, and a second decoding circuit for receiving a second address to enable a selected one of the reading/writing circuits corresponding to said second address.
摘要翻译：用于半导体存储器件的解码电路和方法通过单独执行大块解码和小块解码操作简化了解码处理，从而减少了地址解码处理和解码电路所占用的布局区域的总时延。一种具有包括多个大块的存储单元阵列的半导体存储器件的解码电路，每个大块包括m个小块（其中m = 2,3，...），并且具有多个存储单元矩阵形式和与所述大块相对应的多个读/写电路包括：第一解码电路，用于接收第一地址以同时选择对应于第一地址的每个大块中的相应特定小块，以及第二解码电路，用于接收第二地址以使得对应于所述第二地址的所述读/写电路中的所选择的一个。

74. 发明申请

US20120224437A1 NON-VOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT WITH AN IMPROVED WRITE PERFORMANCE 有权
标题翻译：使用具有改进的写性能的可变电阻元件的非易失性存储器件
公开(公告)号：US20120224437A1
公开(公告)日：2012-09-06
申请号：US13470617
申请日：2012-05-14
申请人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
发明人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C7/1078 , G11C7/1096 , G11C8/10 , G11C11/22 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0088 , G11C2013/009 , G11C2213/72
摘要： A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为产生第一电压的第一电压发生器，被配置为接收具有高于第一电压的电平的外部电压的电压焊盘写入驱动器，被配置为被提供有所述外部电压并被配置为向从所述存储单元阵列中选择的所述多个非易失性存储器单元写入数据; 感测放大器，被配置为被提供有外部电压并且被配置为从从存储单元阵列中选择的多个非易失性存储器单元读取数据;行解码器和列解码器，被配置为选择多个非易失性存储器包括在存储单元阵列中的单元，行解码器被提供有第一电压，并且列解码器被提供有外部电压。

75. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

76. 发明申请

US20100097850A1 APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES 有权
标题翻译：使用相变记忆的装置和系统
公开(公告)号：US20100097850A1
公开(公告)日：2010-04-22
申请号：US12611606
申请日：2009-11-03
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

77. 发明申请

US20090161419A1 NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 失效
标题翻译：非易失性存储器，存储器系统和驱动方法
公开(公告)号：US20090161419A1
公开(公告)日：2009-06-25
申请号：US12339204
申请日：2008-12-19
申请人： Joon-Min PARK , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min PARK , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C11/00 , G11C11/416
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元使用外部提供的升压电压。

78. 发明申请

US20090154221A1 Non-Volatile memory device using variable resistance element with an improved write performance 有权
标题翻译：使用可变电阻元件的非易失性存储器件具有改进的写入性能
公开(公告)号：US20090154221A1
公开(公告)日：2009-06-18
申请号：US12314513
申请日：2008-12-11
申请人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
发明人： Hye-Jin Kim , Kwang-Jin Lee , Du-Eung Kim , Hung-Jun An
IPC分类号： G11C11/00 , G11C7/00 , G11C5/14
CPC分类号： G11C7/1078 , G11C5/14 , G11C7/1096 , G11C13/00 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件。非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘，读出放大器提供第一电压并从存储单元阵列中选择的非易失性存储单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储单元阵列中选择的非易失性存储单元。

79. 发明授权

US07471553B2 Phase change memory device and program method thereof 有权
标题翻译：相变存储器件及其编程方法
公开(公告)号：US07471553B2
公开(公告)日：2008-12-30
申请号：US11319373
申请日：2005-12-29
申请人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
发明人： Kwang-Jin Lee , Du-Eung Kim , Sang-Beom Kang , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.
摘要翻译：相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路编程间隔。泵电路响应于外部控制信号在编程间隔之前被激活。

80. 发明授权

US07304885B2 Phase change memories and/or methods of programming phase change memories using sequential reset control 有权
标题翻译：相变存储器和/或使用顺序复位控制编程相变存储器的方法
公开(公告)号：US07304885B2
公开(公告)日：2007-12-04
申请号：US11074557
申请日：2005-03-08
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Phase-change memory devices are provided that include a plurality of phase-change memory cells and a reset pulse generation circuit configured to output a plurality of sequential reset pulses. Each sequential reset pulse is output to a corresponding one of a plurality of reset lines. A plurality of write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit. Methods of programming phase-change memory devices using sequential reset control signals are also provided.
摘要翻译：提供了包括多个相变存储器单元的相变存储器件和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多条复位线中相应的一条。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。还提供了使用顺序复位控制信号编程相变存储器件的方法。

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