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71. 发明授权

US5037506A Method of stripping layers of organic materials 失效
标题翻译：剥离有机材料层的方法
公开(公告)号：US5037506A
公开(公告)日：1991-08-06
申请号：US579064
申请日：1990-09-06
申请人： Subhash Gupta , Bhanwar Singh , Ahmad Waleh
发明人： Subhash Gupta , Bhanwar Singh , Ahmad Waleh
IPC分类号： G03F7/42 , H01L21/306 , H01L21/311 , H05K3/26
CPC分类号： H01L21/02046 , G03F7/42 , H01L21/31138 , H05K3/26 , Y10S134/902 , Y10S438/906
摘要： Gaseous sulfur trioxide is used to remove various organic coatings, polymerized photoresist, and especially implant and deep-UV hardened photoresist layers, during the manufacture of semiconductor or ceramic devices.
摘要翻译：在制造半导体或陶瓷器件期间，使用气态三氧化硫去除各种有机涂层，聚合光致抗蚀剂，特别是植入物和深UV固化的光致抗蚀剂层。

72. 发明授权

US06515342B1 Method and system for providing inorganic vapor surface treatment for photoresist adhesion promotion 失效
标题翻译：提供无机蒸汽表面处理用于光刻胶粘附促进的方法和系统
公开(公告)号：US06515342B1
公开(公告)日：2003-02-04
申请号：US09557680
申请日：2000-04-25
申请人： Subhash Gupta , Bhanwar Singh , Carmen Morales
发明人： Subhash Gupta , Bhanwar Singh , Carmen Morales
IPC分类号： H01L2900
CPC分类号： G03F7/16 , H01L21/02134 , H01L21/02271 , H01L21/02282 , H01L21/0274 , H01L21/31138 , H01L21/31144 , H01L21/3124
摘要： A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.
摘要翻译：公开了一种用于在低介电常数层中形成多个结构的系统和方法。低介电常数层设置在半导体上。所述方法和系统包括将低介电常数层暴露于改善光致抗蚀剂的粘附性的试剂，在低介电常数层上提供光致抗蚀剂层，图案化光致抗蚀剂，以及蚀刻低介电常数层以形成多个结构。

73. 发明授权

US06313018B1 Process for fabricating semiconductor device including antireflective etch stop layer 有权
标题翻译：用于制造包括抗反射蚀刻停止层的半导体器件的工艺
公开(公告)号：US06313018B1
公开(公告)日：2001-11-06
申请号：US09504449
申请日：2000-02-16
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L2120
CPC分类号： H01L21/0214 , H01L21/02126 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量的硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

74. 发明授权

US06172421B2 Semiconductor device having an intermetallic layer on metal interconnects 有权
标题翻译：在金属互连上具有金属间层的半导体器件
公开(公告)号：US06172421B2
公开(公告)日：2001-01-09
申请号：US09132282
申请日：1998-08-11
申请人： Paul Raymond Besser , Shekhar Pramanick , Takeshi Nogami , Subhash Gupta
发明人： Paul Raymond Besser , Shekhar Pramanick , Takeshi Nogami , Subhash Gupta
IPC分类号： H01L2348
CPC分类号： H01L21/76858 , H01L21/76849 , H01L21/76886
摘要： The present invention relates to the formation of a protective intermetallic layer 15 on the surface of damascene metal interconnects 12 during semiconductor fabrication. The intermetallic layer 15 prevents problems associated with formation of an oxide layer on the surface of the interconnect. The intermetallic layer is formed by depositing a metal on the surface of the interconnect that will both reduce any present metal oxide layer and form an intermetallic with the interconnect metal.
摘要翻译：本发明涉及在半导体制造期间在镶嵌金属互连件12的表面上形成保护性金属间化合物层15。金属间层15防止与互连表面上形成氧化物层有关的问题。金属间化合物层通过在互连表面上沉积金属而形成，该金属将既减少任何存在的金属氧化物层并与互连金属形成金属间化合物。

75. 发明授权

US6051882A Subtractive dual damascene semiconductor device 失效
标题翻译：减法双镶嵌半导体器件
公开(公告)号：US6051882A
公开(公告)日：2000-04-18
申请号：US905974
申请日：1997-08-05
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Rin Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/52
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76813 , H01L21/76877 , H01L21/76885 , H01L2924/0002
摘要： A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.
摘要翻译：一种制造导线的互连电平的方法，以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法，其使用反向镶嵌来形成导电线和通孔。首先使用导电线图案来完全蚀刻该层以形成导电线开口。开口完全被导电材料填充并平坦化，使得导电材料和绝缘层的表面是共面的。通孔图案垂直于导电线对齐，并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。由此在导电线的上部形成的开口用绝缘材料填充，以完成与绝缘层下部的导电线和层的上部向上突出的通孔的双镶嵌互连水平。此外，通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

76. 发明授权

US5994206A Method of forming a high conductivity metal interconnect using metal gettering plug and system performing the method 失效
标题翻译：使用金属吸气塞形成高导电性金属互连的方法和执行该方法的系统
公开(公告)号：US5994206A
公开(公告)日：1999-11-30
申请号：US944170
申请日：1997-10-06
申请人： Subhash Gupta , Susan Hsuching Chen
发明人： Subhash Gupta , Susan Hsuching Chen
IPC分类号： H01L21/768 , H01L21/225 , H01L21/385
CPC分类号： H01L21/76877 , H01L21/76802
摘要： A method and system for providing a via structure for a high conductivity metal of a integrated circuit is disclosed. In a first aspect the method and system comprises etching a photoresist material and a dielectric material down to the high conductivity metal to form a via hole. The via hole includes sputtered high conductivity metal on the sidewalls. The method and system further includes providing a via plug material within the via hole. The vial plug material substantially covers a base portion of the high conductivity metal and the sidewalls of the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the dielectric material. In a second aspect, a via structure for an integrated circuit is disclosed in accordance with the present invention. The via structure includes a high conductivity metal and a dielectric material surrounding the high conductivity metal. The dielectric material includes sidewalls to form a via hole on tope of the high conductivity metal. The via structure further includes a via plug material covering the high conductivity metal and substantially filling the via hole. The via plug material is also capable of gettering or dissolving the high conductivity metal sputtered on the sidewalls of the via hole. Accordingly, by providing a via plug material within the via hole, the via plug material getters or dissolves the high conductivity metal that reaches the sidewalls of the dielectric layer during the via etch and sputter etch processes and the junction poisoning problems associated therewith are substantially minimized.
摘要翻译：公开了一种用于为集成电路的高导电性金属提供通孔结构的方法和系统。在第一方面，该方法和系统包括将光致抗蚀剂材料和电介质材料蚀刻到高导电性金属上以形成通孔。通孔包括在侧壁上的溅射的高导电性金属。该方法和系统还包括在通孔内提供通孔塞材料。小瓶插头材料基本上覆盖高导电性金属的基部和通孔的侧壁。通孔插塞材料还能够吸收或溶解溅射在电介质材料的侧壁上的高导电性金属。在第二方面中，根据本发明公开了一种用于集成电路的通孔结构。通孔结构包括高导电性金属和围绕高导电性金属的介电材料。电介质材料包括在高导电性金属的顶部上形成通孔的侧壁。通孔结构还包括覆盖高导电性金属并基本上填充通孔的通孔塞材料。通孔插塞材料还能够吸收或溶解溅射在通孔的侧壁上的高导电性金属。因此，通过在通孔内提供通孔插塞材料，通孔插塞材料在通孔蚀刻和溅射蚀刻工艺期间吸收或溶解到达介电层侧壁的高导电性金属，并且与之相关的结中毒问题基本上最小化。

77. 发明授权

US5926690A Run-to-run control process for controlling critical dimensions 失效
标题翻译：用于控制关键尺寸的运行控制过程
公开(公告)号：US5926690A
公开(公告)日：1999-07-20
申请号：US864489
申请日：1997-05-28
申请人： Anthony John Toprac , Douglas John Downey , Subhash Gupta
发明人： Anthony John Toprac , Douglas John Downey , Subhash Gupta
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/20
摘要： It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time of photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a manipulated variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits. Polysilicon gate linewidth variability is reduced using a control method using either feedforward and feedback or feedback alone. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist etch time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power as a manipulated variable. A run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis. The run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification. The run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.
摘要翻译：已经发现，已知和未知的关键尺寸变化的所有原因通过调整光致抗蚀剂蚀刻的时间来补偿。因此，控制方法采用使用光致抗蚀剂蚀刻时间的控制系统作为前馈或反馈控制配置中的操纵变量来控制半导体制造期间的临界尺寸变化。通过调整光致抗蚀剂蚀刻时间来控制关键尺寸，实现了许多优点，包括减少的批次批量变化，增加的产量和增加的制造电路的速度。在一个实施例中，对微处理器电路中的多晶硅栅极关键尺寸控制实现了这些优点。使用仅使用前馈和反馈或反馈的控制方法来减少多晶硅栅极线宽变化。在一些实施例中，实施反馈控制以使用光致抗蚀剂蚀刻时间来控制临界尺寸作为操纵变量。在替代实施例中，使用RF功率作为操纵变量来控制临界尺寸。运行运行控制技术用于将集成电路的关键尺寸驱动到设定规格。在运行到运行的控制技术中，进行晶片测试或测量，并且基于逐个运行的测试或测量的结果来调整过程控制配方。运行运行控制技术用于将多晶硅栅极结构的关键尺寸驱动到目标规格。应用运行控制技术将集成电路中的关键尺寸驱动到使用光刻胶蚀刻时间作为操作变量的规定规格。

78. 发明授权

US5910453A Deep UV anti-reflection coating etch 失效
标题翻译：深UV抗反射涂层蚀刻
公开(公告)号：US5910453A
公开(公告)日：1999-06-08
申请号：US584941
申请日：1996-01-16
申请人： Subhash Gupta , Mutya Vicente
发明人： Subhash Gupta , Mutya Vicente
IPC分类号： H01L21/027 , H01L21/308 , H01L21/311 , H01L21/312 , H01L21/302
CPC分类号： H01L21/0276 , H01L21/3081 , H01L21/31144 , H01L21/31116 , H01L21/312
摘要： An etching process for DUV photolithography is provided for etching a layer of anti-reflection coating (ARC) comprising spin-on organic ARC material which is formed beneath a layer of photoresist. After patterning the layer of photoresist, the layer of ARC is etched by employing a mixture of oxygen plasma, nitrogen plasma, and at least one inert gas. Anisotropic etching of the layer of ARC is provided with the process of the present invention. In comparison with prior art etching processes for etching a layer of ARC, the process of the present invention provides a favorable etch rate with improved selectivity over the etching of the layer of photoresist. The layer of ARC is etched without causing lateral erosion of the layer of photoresist. Faceting of the top edges of the corners of the layer of photoresist is also minimized. The profile of the layer of photoresist is essentially maintained thereby enabling for critical dimension fidelity. The process of the present invention is residue-free, and provides favorable selectivity for etching the layer of ARC over most underlying materials conventionally used in integrated circuit structures. The layer of ARC can also be etched by employing a mixture of nitrogen plasma and inert gas. Employing a mixture of nitrogen plasma and inert gas, without oxygen plasma, provides a reduced etch rate.
摘要翻译：提供了用于DUV光刻的蚀刻工艺，用于蚀刻包含形成在光致抗蚀剂层下面的旋涂有机ARC材料的抗反射涂层（ARC）层。在图案化光致抗蚀剂层之后，通过使用氧等离子体，氮等离子体和至少一种惰性气体的混合物蚀刻ARC层。本发明的方法提供了ARC层的各向异性蚀刻。与用于蚀刻ARC层的现有技术的蚀刻工艺相比，本发明的方法提供了对蚀刻光致抗蚀剂层的优选蚀刻速率。蚀刻ARC层，不会引起光致抗蚀剂层的横向侵蚀。光致抗蚀剂层的角部的顶部边缘的表面也被最小化。基本上保持光致抗蚀剂层的轮廓，从而能够实现临界尺寸保真度。本发明的方法是无残留的，并且为通常用于集成电路结构的大多数底层材料提供了对ARC层蚀刻的良好选择性。也可以通过使用氮等离子体和惰性气体的混合物来蚀刻ARC层。使用无等离子体的氮等离子体和惰性气体的混合物提供降低的蚀刻速率。

79. 发明授权

US5770519A Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
标题翻译：用于减少与半导体器件中的导电通孔相关的电迁移效应的铜储存器
公开(公告)号：US5770519A
公开(公告)日：1998-06-23
申请号：US464305
申请日：1995-06-05
申请人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
发明人： Richard K. Klein , Darrell Erb , Steven Avanzino , Robin Cheung , Scott Luning , Bryan Tracy , Subhash Gupta , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76831 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L2924/0002
摘要： A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.
摘要翻译：多层半导体结构包括导电通孔。导电通孔包括具有高抗电迁移性的金属储存器。储存器由铜的共形层或沉积在通孔上的金形成，以形成位于通孔中的铜或金塞。在储存器和绝缘层之间设置阻挡层，以防止储存器扩散到绝缘层中。可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积阻挡层和储层。可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和储存器。

80. 发明授权

US5686354A Dual damascene with a protective mask for via etching 失效
标题翻译：双镶嵌带防蚀口罩，用于通孔蚀刻
公开(公告)号：US5686354A
公开(公告)日：1997-11-11
申请号：US478324
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76831 , H01L21/76807
摘要： A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used to form conductive line openings in an insulating layer. Next, a thin protective layer of conformal material is deposited in the conducive line opening. The protective layer and the insulating layer each have etch resistance to others etchant. Using a via mask pattern, openings are etching the protective layer with the insulating layer serving as and etch stop. Next via openings are etched in the insulating material using the openings in the thin protective layer as the etch mask. If the protective layer is a conductive material, it is removed from the surface of the insulating layer either before or after the conductive line and via openings are filled with a conductive material. If the protective material is an insulating material, it is entirely removed before filling the conductive line and via openings conductive material.
摘要翻译：一种双镶嵌方法，用于制造导线的互连级别并且连接用于集成电路的绝缘和用于半导体器件的衬底载体的通孔，其使用薄的保护性通孔掩模形成通孔。导电线掩模图案用于在绝缘层中形成导电线路开口。接下来，在导电线路开口中沉积有保形材料的薄保护层。保护层和绝缘层各自具有对其它蚀刻剂的耐蚀刻性。使用通孔掩模图案，开口蚀刻保护层，绝缘层用作蚀刻停止。接下来通过开口被蚀刻在绝缘材料中，使用薄保护层中的开口作为蚀刻掩模。如果保护层是导电材料，则在导电线之前或之后将其从绝缘层的表面去除，并且通孔开口填充有导电材料。如果保护材料是绝缘材料，则在填充导电线和通孔开口导电材料之前将其完全去除。

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