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71. 发明授权

US5061925A Phase equalization system for a digital-to-analog converter utilizing separate digital and analog sections 失效
标题翻译：使用单独的数字和模拟部分的数模转换器的相位均衡系统
公开(公告)号：US5061925A
公开(公告)日：1991-10-29
申请号：US571376
申请日：1990-08-22
申请人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
发明人： Navdeep S. Sooch , Donald A. Kerth , Eric J. Swanson , Tetsurou Sugimoto
IPC分类号： H03M1/66 , H03H17/00 , H03H17/02 , H03H17/06 , H03M3/02 , H03M7/00 , H03M7/32
CPC分类号： H03M3/37 , H03M3/50 , H03M7/3028 , H03M7/3035 , H03M7/3037
摘要： A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase provided by the combination of the phase equalization in the digital section (10) and the phase nonlinearity in the analog section (12) will result in a linear overall phase relationship for the DAC.
摘要翻译：用于数模转换器（DAC）的相位均衡系统包括具有插值部分（14）的数字部分（10），用于接收数字输入并增加其采样频率以输入到Δ-Σ调制器（16 ）。在插值电路（14）和Δ-Σ调制器（16）之间设置加法结（24），以允许偏移电压与其相加。这提供直流偏移，该偏移由校准控制（40）控制。数字部分（10）的输出被输入到模拟部分（12）中，模拟部分（12）具有一个比特DAC21），该模拟部分（12）被输入到模拟滤波器（22），用于转换和滤波由 Δ-Σ调制器（16）。内插电路（14）包括三级内插滤波器，包括第一级（50），第二级（52）和第三级（54）。第二级（52）由具有非线性相位响应的有限脉冲响应滤波器（FIR）组成。内插滤波器（52）的非线性相位响应补偿模拟滤波器（22）与线性相位响应的相位偏差。因此，通过数字部分（10）中的相位均衡和模拟部分（12）中的相位非线性的组合提供的复合相位将导致DAC的线性整体相位关系。

72. 发明授权

US4588941A Cascode CMOS bandgap reference 失效
标题翻译： Cascode CMOS带隙参考
公开(公告)号：US4588941A
公开(公告)日：1986-05-13
申请号：US700600
申请日：1985-02-11
申请人： Donald A. Kerth , Navdeep S. Sooch
发明人： Donald A. Kerth , Navdeep S. Sooch
IPC分类号： G05F3/24 , G05F3/30 , G05F3/20
CPC分类号： G05F3/30 , Y10S323/907
摘要： A CMOS bandgap voltage reference which is temperature stable is disclosed. The large temperature-dependent p-tub resistors of prior art arrangements are replaced with relatively small, temperature stable p+ diffusion resistors. The increase in current level needed to compensate for the decrease in resistor value is provided by a simple cascode MOS circuit located between the ratioing resistors and the VSS potential.
摘要翻译：公开了一种温度稳定的CMOS带隙电压基准。现有技术的大型温度依赖性p型电位器替换为相对较小的温度稳定的p +扩散电阻器。通过位于比电阻和VSS电位之间的简单共源共栅MOS电路来提供补偿电阻值下降所需的电流增加。

73. 发明授权

US4583037A High swing CMOS cascode current mirror 失效
标题翻译：高频CMOS共源共栅电流镜
公开(公告)号：US4583037A
公开(公告)日：1986-04-15
申请号：US643636
申请日：1984-08-23
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03F3/343 , G05F3/26 , H03F3/16 , H03F3/34 , H03F3/345
CPC分类号： G05F3/262
摘要： A CMOS cascode current mirror exhibits an input side voltage swing equal to V.sub.T +2V.sub.ON and provides virtually no mismatch between the input and output currents. A negative feedback loop (52) comprising a plurality of MOS transistors is utilized to provide the voltages necessary for good current matching (V.sub.T +2V.sub.ON, V.sub.T +V.sub.ON) and to maintain the transistors of the input circuit branch in their saturation region of operation. By maintaining the input transistors in saturation, the output current will track the input current, regardless of increases in ambient temperature or the value of threshold voltage V.sub.T.
摘要翻译： CMOS共源共栅电流镜表现出等于VT + 2VON的输入侧电压摆幅，实际上输入和输出电流之间不会出现失配。使用包括多个MOS晶体管的负反馈环路（52）来提供良好电流匹配（VT + 2VON，VT + VON）所需的电压并且将输入电路的晶体管保持在饱和操作区域。通过将输入晶体管保持在饱和状态，输出电流将跟踪输入电流，而不考虑环境温度的升高或阈值电压VT的值。

74. 发明授权

US5767722A Delta sigma switch capacitor filter using curent feed forward 失效
标题翻译：三角形开关电容滤波器采用向前馈送
公开(公告)号：US5767722A
公开(公告)日：1998-06-16
申请号：US627752
申请日：1996-04-02
申请人： Dan B. Kasha , Navdeep S. Sooch
发明人： Dan B. Kasha , Navdeep S. Sooch
IPC分类号： H03H19/00 , H03K17/16
CPC分类号： H03H19/004
摘要： An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.
摘要翻译：具有负载有负载阻抗的电路级的诸如开关电容器级或1位数模转换器和开关电容滤波器的电子电路使用电流前馈来基本上消除负载阻抗的影响。一个电路包括一个电路级和负载阻抗跟随并连接到电路级。电流前馈电路连接到负载阻抗，基本上抵消负载阻抗，以提高数模转换器或开关电容滤波器的线性度。

75. 发明授权

US5579247A Method and apparatus for decreasing the interference and noise sensitivity of a ratiometric converter type of circuit 失效
标题翻译：减小比例转换器类型电路的干扰和噪声灵敏度的方法和装置
公开(公告)号：US5579247A
公开(公告)日：1996-11-26
申请号：US537224
申请日：1995-09-29
申请人： Donald A. Kerth , Navdeep S. Sooch
发明人： Donald A. Kerth , Navdeep S. Sooch
IPC分类号： G01R19/00 , G01D3/00 , G01R19/10 , G01R19/25 , H03M1/06 , H03M1/12 , H03M3/00 , G06F19/00
CPC分类号： H03M1/0621 , G01D3/00 , H03M3/324 , H03M1/12 , H03M3/342 , H03M3/458
摘要： A ratiometric converter receives an external sense signal and external reference signal and provides an output signal which is proportional to the sense signal and inversely proportional to the reference signal. Electromagnetic interference and noise coupled onto the sense and reference lines are effectively removed by converting the sense signal to a digital signal and converting the reference signal to a digital signal. The digital sense signal is then filtered through a low pass filter to provide a filtered signal, and similarly, the digital reference signal is filtered through a low pass filter to provide a filtered digital reference signal. A divider circuit then divides the filter digital sense signal by the filter digital reference signal to provide the output signal.
摘要翻译：比例转换器接收外部感测信号和外部参考信号，并提供与感测信号成比例并与参考信号成反比的输出信号。通过将感测信号转换为数字信号并将参考信号转换为数字信号，有效地消除耦合到感测和参考线上的电磁干扰和噪声。然后通过低通滤波器对数字感测信号进行滤波，以提供经过滤波的信号，类似地，数字参考信号通过低通滤波器滤波以提供经过滤波的数字参考信号。分频器电路然后将滤波器数字检测信号除以滤波器数字参考信号以提供输出信号。

76. 发明授权

US5258758A DAC shutdown for low power supply condition 失效
标题翻译： DAC关断低电源条件
公开(公告)号：US5258758A
公开(公告)日：1993-11-02
申请号：US648791
申请日：1991-01-31
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03M1/06 , H02H3/24 , H03M1/00 , H03M1/66
CPC分类号： H03M1/002 , H02H3/24 , H03M1/66 , Y10T307/858
摘要： A digital-to-analog converter for operating in a low power condition includes a delta-sigma modulator (10) for converting an n-bit digital input signal to an m-bit digital output signal. The output signal is filtered with a switched-capacitor filter (12) and an active RC low-pass filter (18). A low power supply detect circuit receives two power supply input voltages, the low and the high power supplies, and outputs a control signal on a line (38) indicating a low power supply condition. The digital-to-analog converter includes an output stage (26) with the analog output thereof being connected to an analog output terminal (30). A switch (28) is provided for connecting the output stage to the analog output terminal (30) in normal operating mode. In a low power mode, the low power detect circuit (20) generates a control signal on line (38) in response to the power supply voltage falling below a predetermined threshold. The switch (28) is opened and a shunt switch (32) provides a squelch operation by being configured in a closed configuration during a low power condition. Alternately, the output stage (26) can be powered down in the low power condition.
摘要翻译：用于在低功率状态下工作的数模转换器包括用于将n位数字输入信号转换成m位数字输出信号的Δ-Σ调制器（10）。输出信号用开关电容滤波器（12）和有源RC低通滤波器（18）滤波。低电源检测电路接收两个电源输入电压，即低电源和高电源，并且在指示低电源条件的线路（38）上输出控制信号。数模转换器包括其模拟输出连接到模拟输出端（30）的输出级（26）。提供了一个开关（28），用于在正常操作模式下将输出级与模拟输出端（30）相连。在低功率模式下，响应于电源电压低于预定阈值，低功率检测电路（20）在线（38）上产生一个控制信号。开关（28）打开，并且分流开关（32）通过在低功率状态下被配置为闭合配置来提供静噪操作。或者，输出级（26）可以在低功率状态下掉电。

77. 发明授权

US5245344A High order switched-capacitor filter with DAC input 失效
标题翻译：具有DAC输入的高阶开关电容滤波器
公开(公告)号：US5245344A
公开(公告)日：1993-09-14
申请号：US641183
申请日：1991-01-15
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03H19/00 , H03M1/66 , H03M3/02 , H03M7/00
CPC分类号： H03H19/004
摘要： A digital-to-analog converter includes a delta-sigma modulator (10) that receives a digital input and converts it to a one-bit digital output stream. A fourth order switched-capacitor filter (12) is operable to receive the one-bit digital stream and convert it to an analog value int he sampled data domain. This is input to a switched-capacitor/continuous time buffer (14) which is then filtered by an active low pass filter (18) to provide an analog output. The switched-capacitor filter (12) includes four stages of integration (24), (30), (34) and (38). A one-bit DAC (20) is provided for converting the one-bit digital stream to an analog value. The one-bit DAC (20) is integral with the first stage of integration and is summed by a summing junction (22) with the output of the forth stage of integration (38). In this manner, the first stage of integration (24) is operable to influence or reduce the noise output by the fourth stage of integration (38), thus resulting in a low noise high order switched-capacitor filter.
摘要翻译：数模转换器包括接收数字输入并将其转换为1位数字输出流的Δ-Σ调制器（10）。第四级开关电容滤波器（12）可操作以接收一比特数字流并将其转换成采样数据域中的模拟值。这被输入到开关电容器/连续时间缓冲器（14），然后由有源低通滤波器（18）进行滤波以提供模拟输出。开关电容滤波器（12）包括四级积分（24），（30），（34）和（38）。提供一位DAC（20），用于将一位数字流转换为模拟值。一比特DAC（20）与第一级积分是积分的，并且通过求和结（22）与第四级积分（38）的输出相加。以这种方式，第一级积分（24）可操作以影响或降低第四级积分（38）的噪声输出，从而导致低噪声高阶开关电容滤波器。

78. 发明授权

US4550284A MOS Cascode current mirror 失效
标题翻译： MOS Cascode电流镜
公开(公告)号：US4550284A
公开(公告)日：1985-10-29
申请号：US610881
申请日：1984-05-16
申请人： Navdeep S. Sooch
发明人： Navdeep S. Sooch
IPC分类号： H03F3/343 , G05F3/26 , H01L29/78 , H03F3/34 , H03F3/345 , G05F3/08
CPC分类号： G05F3/262
摘要： An MOS current mirror is disclosed which comprises only two circuit branches and requires only a single reference current. The input circuit branch includes at least four MOS transistors (40, 42, 44, 46) connected in series and the output circuit branch includes at least two MOS transistors (48, 50) interconnected with selected transistors of the input circuit branch. Mirroring of the input current (I.sub.REF) is accomplished by providing a transistor (46, 50) in each circuit branch with identical operating characteristics (V.sub.DS, V.sub.GS). High output impedance is achieved in accordance with the present invention by adjusting the channel constant (Z/L) of another transistor (42) in the input circuit branch to be one-third the value of the channel constant associated with each of the remaining transistors.
摘要翻译：公开了仅包括两个电路分支并且仅需要单个参考电流的MOS电流镜。输入电路支路包括串联连接的至少四个MOS晶体管（40,42,44,46），并且输出电路支路包括与输入电路支路的选定晶体管互连的至少两个MOS晶体管（48,50）。通过在每个电路支路中提供具有相同工作特性（VDS，VGS）的晶体管（46,50）来实现输入电流（IREF）的镜像。根据本发明，通过调节输入电路支路中另一个晶体管（42）的通道常数（Z / L）达到与每个剩余晶体管相关的沟道常数值的三分之一来实现高输出阻抗。

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