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71. 发明申请

US20070233904A1 Auxiliary Writes Over Address Channel 有权
标题翻译：辅助写入地址通道
公开(公告)号：US20070233904A1
公开(公告)日：2007-10-04
申请号：US11468933
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。

72. 发明授权

US07209998B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07209998B2
公开(公告)日：2007-04-24
申请号：US10921053
申请日：2004-08-17
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

73. 发明授权

US07167971B2 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
标题翻译：用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法
公开(公告)号：US07167971B2
公开(公告)日：2007-01-23
申请号：US10881146
申请日：2004-06-30
申请人： Sameh W. Asaad , Richard Gerard Hofmann
发明人： Sameh W. Asaad , Richard Gerard Hofmann
IPC分类号： G06F9/30 , G06F9/00
CPC分类号： G06F9/3885 , G06F8/443 , G06F9/30181 , G06F9/3897
摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
摘要翻译：一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。停止信号被清除，指令被执行。

74. 发明授权

US06970816B1 Method and system for efficiently generating parameterized bus transactions 失效
标题翻译：有效产生参数化总线事务的方法和系统
公开(公告)号：US06970816B1
公开(公告)日：2005-11-29
申请号：US09638268
申请日：2000-08-14
申请人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
发明人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.
摘要翻译：用于有效地产生用于验证被测设计（DUT）的参数化总线事务的方法和系统包括向发生器程序提供DUT的配置文件。配置文件定义可由DUT执行的总线事务的可能参数组合，并且生成器程序系统地枚举所有可能的组合以产生用于验证DUT的测试用例。在配置文件中指定的规则可以包括或排除选定的参数组合，以将测试用例定制到特定的DUT到总线接口。

75. 发明授权

US6047336A Speculative direct memory access transfer between slave devices and memory 失效
标题翻译：从设备和存储器之间的直接存储器访问传输
公开(公告)号：US6047336A
公开(公告)日：2000-04-04
申请号：US39645
申请日：1998-03-16
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.
摘要翻译： DMA控制器响应来自从设备的数据传输请求，启动存储器传送周期并在数据传输完成时通知从设备。为了避免内部总线上的死时钟周期，DMA控制器在通知后启动推测数据传输周期。如果从设备在预定时间内没有请求另一个数据传输，则DMA控制器中止推测数据传输周期。

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