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1. 发明授权

US06055584A Processor local bus posted DMA FlyBy burst transfers 失效
标题翻译：处理器本地总线发送DMA FlyBy突发传输
公开(公告)号：US06055584A
公开(公告)日：2000-04-25
申请号：US975540
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
摘要翻译：提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。从总线控制器还耦合到存储器单元。存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

2. 发明授权

US6047336A Speculative direct memory access transfer between slave devices and memory 失效
标题翻译：从设备和存储器之间的直接存储器访问传输
公开(公告)号：US6047336A
公开(公告)日：2000-04-04
申请号：US39645
申请日：1998-03-16
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.
摘要翻译： DMA控制器响应来自从设备的数据传输请求，启动存储器传送周期并在数据传输完成时通知从设备。为了避免内部总线上的死时钟周期，DMA控制器在通知后启动推测数据传输周期。如果从设备在预定时间内没有请求另一个数据传输，则DMA控制器中止推测数据传输周期。

3. 发明授权

US6032238A Overlapped DMA line transfers 失效
标题翻译：重叠的DMA线路传输
公开(公告)号：US6032238A
公开(公告)日：2000-02-29
申请号：US20123
申请日：1998-02-06
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.
摘要翻译：提供了允许DMA线读取和行写入周期重叠的方法和装置。在示例性实施例中，PLB线读取字地址总线与DMA控制器边带信号一起使用，以检测在线读取周期完成之前允许DMA控制器开始行写入一个周期所需的条件。当读取多字行传输的第一个字时，设置一个参考位。边缘定时信号在读周期完成之前一个周期产生，表示只读一行读取数据相位。如果要在存储器中写入的第一个字已经被读取或在生成定时信号时可用，则在存储器读取传送的最后阶段之前开始写入操作，并且读取和写入操作重叠，从而完成如果顺序完成，则读取/写入传输的循环次数比读取和写入传输周期的总和少。

4. 发明授权

US5884051A System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities 失效
标题翻译：基于固定和动态优先级灵活控制总线访问的系统，方法和计算机程序产品
公开(公告)号：US5884051A
公开(公告)日：1999-03-16
申请号：US874639
申请日：1997-06-13
申请人： Mark Michael Schaffer , James N. Dieffenderfer , Edward Hammond Green, III , Juan Guillermo Revilla
发明人： Mark Michael Schaffer , James N. Dieffenderfer , Edward Hammond Green, III , Juan Guillermo Revilla
IPC分类号： G06F13/364 , G06F13/18 , G06F13/362
CPC分类号： G06F13/364
摘要： Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by providing a flexible bus arbiter. Bus access is controlled using a bus arbiter which is operationally connected to each of the devices. Each device has a fixed programmable priority level and a dynamic priority level associated with it. The dynamic priority level comprises an arbiter dynamic priority level and a master dynamic priority level. Access to the bus by a device is controlled based on the combination of the programmable fixed priority level and the dynamic priority level associated with each device. While the programmable fixed priority level and the arbiter dynamic priority level as set by the arbiter are not controlled by the master, the master dynamic priority level is controlled by the master. If master dynamic priority is enabled, it overrides the arbiter dynamic priority level. If master dynamic priority is not enabled but arbiter dynamic priority is enabled, master dynamic priority overrides the programmable fixed priority level.
摘要翻译：可以通过提供灵活的总线仲裁器来改进具有访问公共共享总线的多个设备的计算机系统中的总线性能。总线访问使用总线仲裁器进行控制，总线仲裁器可操作地连接到每个设备。每个设备具有固定的可编程优先级和与之相关联的动态优先级。动态优先级包括仲裁器动态优先级和主动态优先级。基于可编程固定优先级与与每个设备相关联的动态优先级的组合来控制设备对总线的访问。虽然由仲裁器设置的可编程固定优先级和仲裁器动态优先级不受主控制，主动态优先级由主控制。如果启用主动态优先级，它将覆盖仲裁器动态优先级。如果未启用主动态优先级，但启用仲裁动态优先级，则主动态优先级将覆盖可编程固定优先级。

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