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71. 发明授权

US07732841B2 Pixel sensor cell for collecting electrons and holes 有权
标题翻译：用于收集电子和空穴的像素传感器单元
公开(公告)号：US07732841B2
公开(公告)日：2010-06-08
申请号：US12172309
申请日：2008-07-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L27/148 , H01L31/062
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明是像素传感器单元及其制造方法。像素传感器单元对于给定的光量大约使可用信号加倍。本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上产生的电子以及形成在基板表面下方的p型收集阱区域用于收集由撞击光子产生的孔。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

72. 发明授权

US07692254B2 Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure 有权
标题翻译：具有合并源极/漏极硅化物的鳍型场效应晶体管结构和形成结构的方法
公开(公告)号：US07692254B2
公开(公告)日：2010-04-06
申请号：US11778217
申请日：2007-07-16
申请人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive material (e.g., a metal silicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions. Merging the semiconductor fins in this manner also allows each of the source/drain regions to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（即，多鳍式双栅极或三栅极场效应晶体管）的实施例，其中多个散热片部分或完全由高导电材料（例如，金属硅化物）。以这种方式合并散热片使串联电阻最小化，栅极和源极/漏极区之间的寄生电容几乎不增加。以这种方式合并半导体散热片也允许每个源极/漏极区域通过单个触点通孔接触，以及该触点通孔的更灵活的放置。

73. 发明授权

US07655966B2 High efficiency CMOS image sensor pixel employing dynamic voltage supply 有权
标题翻译：采用动态电压源的高效率CMOS图像传感器像素
公开(公告)号：US07655966B2
公开(公告)日：2010-02-02
申请号：US12050967
申请日：2008-03-19
申请人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Mark D. Jaffe , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N3/14
CPC分类号： H04N5/361 , G06F17/5063 , H04N5/359 , H04N5/3745
摘要： A global shutter compatible pixel circuit comprising a reset gate (RG) transistor is provided in which a dynamic voltage is applied to the drain of the reset gate transistor in order to reduce a floating diffusion (FD) leakage therethrough during signal hold time. The drain voltage of the reset gate transistor is held at a lower voltage than a circuit supply voltage to minimize the off-state leakage through the RG transistor, thus reducing the change in the voltage at the floating diffusion during the signal hold time. In addition, a design structure for such a circuit providing a dynamic voltage to the drain of a reset gate of a pixel circuit is also provided.
摘要翻译：提供了包括复位栅极（RG）晶体管的全局快门兼容像素电路，其中动态电压被施加到复位栅极晶体管的漏极，以便减少在信号保持时间期间通过其的浮动扩散（FD）泄漏。复位栅极晶体管的漏极电压保持在比电路电源电压更低的电压，以最小化通过RG晶体管的截止状态泄漏，从而减少信号保持时间期间浮动扩散时的电压变化。此外，还提供了用于向像素电路的复位栅极的漏极提供动态电压的这种电路的设计结构。

74. 发明授权

US07633042B2 Pixel sensor cell having a pinning layer surrounding collection well regions for collecting electrons and holes 失效
标题翻译：像素传感器单元具有围绕用于收集电子和空穴的收集阱区的钉扎层
公开(公告)号：US07633042B2
公开(公告)日：2009-12-15
申请号：US12172306
申请日：2008-07-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Lolseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Lolseau
IPC分类号： H01L27/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明是像素传感器单元及其制造方法。像素传感器单元对于给定的光量大约使可用信号加倍。本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上产生的电子以及形成在基板表面下方的p型收集阱区域用于收集由撞击光子产生的孔。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

75. 发明申请

US20090065818A1 STRUCTURE FOR IMAGERS HAVING ELECTRICALLY ACTIVE OPTICAL ELEMENTS 有权
标题翻译：具有电活动光学元件的图像的结构
公开(公告)号：US20090065818A1
公开(公告)日：2009-03-12
申请号：US11850807
申请日：2007-09-06
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L27/146
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14636
摘要： A design structure embodied in a machine readable medium for use in a design process, the design structure representing a CMOS image sensor device comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical functions. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.
摘要翻译：体现在用于设计过程的机器可读介质中的设计结构，该设计结构表示包括有源像素单元阵列的CMOS图像传感器设备。每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。形成的透光导线结构提供电和光学功能。通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。用于导线层的电气功能包括用作电容器板，电阻器或互连件。

76. 发明申请

US20080144240A1 Electro-Static Discharge Protection Circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US20080144240A1
公开(公告)日：2008-06-19
申请号：US11612033
申请日：2006-12-18
申请人： John J. Ellis-Monaghan , Steven H. Voldman
发明人： John J. Ellis-Monaghan , Steven H. Voldman
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An electrostatic-discharge protection circuit having a low level of current leakage from a first power supply to a second power supply. An example protection circuit includes a timing element that electrically decouples the first and second power supplies. Another example protection circuit includes two transistors connected via a node that is electrically decoupled from the second power supply.
摘要翻译：一种具有从第一电源到第二电源的低电流泄漏的静电放电保护电路。示例性保护电路包括电分离第一和第二电源的定时元件。另一个示例性保护电路包括经由与第二电源电分离的节点连接的两个晶体管。

77. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

78. 发明授权

US08743247B2 Low lag transfer gate device 有权
标题翻译：低延迟传输门装置
公开(公告)号：US08743247B2
公开(公告)日：2014-06-03
申请号：US12013826
申请日：2008-01-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan
IPC分类号： H04N3/14 , H01L31/062
CPC分类号： H01L31/103 , H04N5/353 , H04N5/374 , H04N5/3745
摘要： A method of forming a CMOS active pixel sensor (APS) cell structure having at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure. Alternately, an intermediate charge storage device and second transfer gate device may be provided which may first temporarily receive charge carriers from the photosensing device, and, upon activating the second transfer gate device in a further timed fashion, read out the charge stored at the intermediate charge storage device for transfer to the second transfer gate device while preventing spillback of charges to the photosensing device. The APS cell structure is further adapted for a global shutter mode of operation, and further comprises a light shield element is further provided to ensure no light reaches the photosensing and charge storage devices during charge transfer operation.
摘要翻译：一种形成具有至少一个传输栅极器件和操作方法的CMOS有源像素传感器（APS）单元结构的方法。第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。或者，可以提供中间电荷存储装置和第二传输门装置，其可以首先临时从光敏装置接收电荷载体，并且在以另外的定时方式激活第二传输门装置时，读出存储在中间电荷存储装置，用于传送到第二传输门装置，同时防止电荷向光感器件溢出。 APS单元结构进一步适用于全局快门操作模式，并且进一步包括遮光元件，以在电荷转移操作期间确保没有光到达光敏和电荷存储装置。

79. 发明授权

US08698244B2 Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method 有权
标题翻译：绝缘体上硅（SOI）结构配置为减少谐波，设计结构和方法
公开(公告)号：US08698244B2
公开(公告)日：2014-04-15
申请号：US12634893
申请日：2009-12-10
申请人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
发明人： Alan B. Botula , John J. Ellis-Monaghan , Alvin J. Joseph , Max G. Levy , Richard A. Phelps , James A. Slinkman , Randy L. Wolf
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203
摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.
摘要翻译：公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。本文还公开了用于这种半导体结构的方法和设计结构的实施例。

80. 发明授权

US08610174B2 Bipolar transistor with a raised collector pedestal for reduced capacitance 有权
标题翻译：双极晶体管带有集电极基座，用于降低电容
公开(公告)号：US08610174B2
公开(公告)日：2013-12-17
申请号：US13307412
申请日：2011-11-30
申请人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
发明人： James W. Adkisson , John J. Ellis-Monaghan , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L31/109
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed is a transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译：公开了具有降低的集电极基座的晶体管，用于减小基极 - 集电极结电容。凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列，收集区域。本征基层在凸起的收集器基座和介电层之上。外在基层在本征基层之上。因此，外部基极层和副集电极区域之间的空间增加。该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。因此，集电极结电容减小，因此最大振荡频率增加。

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