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71. 发明申请

US20080265281A1 EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER 有权
标题翻译：嵌入式硅胶锗，使用双层氧化硅绝缘体
公开(公告)号：US20080265281A1
公开(公告)日：2008-10-30
申请号：US12169674
申请日：2008-07-09
申请人： Huajie Chen , Dureseti Chidambarrao , Dominic J. Schepis , Henry K. Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Dominic J. Schepis , Henry K. Utomo
IPC分类号： H01L27/12
CPC分类号： H01L29/7842 , H01L27/1203 , H01L29/66628 , H01L29/66636 , H01L29/7848 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.
摘要翻译：公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。第二掩埋氧化物层隔离pFET。

72. 发明申请

US20080246019A1 DEFECT REDUCTION BY OXIDATION OF SILICON 有权
标题翻译：通过氧化硅减少缺陷
公开(公告)号：US20080246019A1
公开(公告)日：2008-10-09
申请号：US12139080
申请日：2008-06-13
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/15 , H01L29/165
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

73. 发明申请

US20080064197A1 STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SiGe AND/OR Si:C 有权
标题翻译：用于制造SiGe和/或Si：C的栅极应力工程的散装硅和SOI MOS器件中的分离自由应力通道的结构和方法
公开(公告)号：US20080064197A1
公开(公告)日：2008-03-13
申请号：US11931387
申请日：2007-10-31
申请人： Huilong Zhu , Bruce Doris , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Huajie Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/7845 , H01L21/28035 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/4925 , H01L29/66545 , H01L29/7842
摘要： Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.
摘要翻译：公开了通过具有SiGe和/或Si：C的栅极应力工程的体硅和SOI（绝缘体上硅）CMOS（互补金属氧化物半导体）器件中的无位错应力通道的结构和方法。 CMOS器件包括块体Si或SOI的衬底，衬底上的栅极介电层，以及SiGe和/或Si：C的层叠栅极结构，其具有在SSi（应变Si）/ SiGe或SSi的界面处产生的应力 / Si：C在堆叠栅结构中。层叠栅极结构在栅介质层上具有大晶粒尺寸的Si或SiGe的第一应力膜层，在第一应力膜层上的应变SiGe或应变Si：C的第二应力膜层，以及半导体或导体 p（聚）-Si在第二应力膜层上。

74. 发明授权

US07288827B2 Self-aligned mask formed utilizing differential oxidation rates of materials 有权
标题翻译：使用材料的不同氧化速率形成的自对准掩模
公开(公告)号：US07288827B2
公开(公告)日：2007-10-30
申请号：US10969718
申请日：2004-10-20
申请人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
发明人： Huajie Chen , Kathryn T. Schonenberg , Gregory G. Freeman , Andreas D. Stricker , Jae-Sung Rieh
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L29/66242 , H01L21/32105 , Y10S438/911
摘要： A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation. This self-aligned oxide mask blocks B diffusion from the raised extrinsic base to the corner of collector.
摘要翻译：使用不同材料的不同氧化速率形成自对准氧化物掩模。自对准氧化物掩模形成在CVD生长的基底NPN基层上，其牺牲了场上的活性区域上的单晶Si（或Si / SiGe）和多晶Si（或Si / SiGe）。通过利用多晶硅（或Si / SiGe）比单晶Si（或Si / SiGe）更快地氧化的事实来制造自对准掩模。通过使用热氧化工艺在多晶硅（或Si / siGe）和单晶Si（或Si / siGe）上形成氧化膜，以在多晶硅（或Si / SiGe）上形成厚的氧化层，以及在单晶Si（或Si / siGe）上方的薄氧化层，随后进行受控氧化物蚀刻以除去单晶Si（或Si / siGe）上的薄氧化层，同时将自对准氧化物掩模层留在多晶硅（或Si / siGe）。然后在自对准掩模形成之后形成隆起的外在基体。该自对准氧化物掩模阻挡从扩展的外在碱基到收集器角的扩散。

75. 发明申请

US20070249114A1 Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions 有权
标题翻译：制造应变半导体晶体管的方法，其具有位于源极和漏极区域之下的晶格失配的半导体区域
公开(公告)号：US20070249114A1
公开(公告)日：2007-10-25
申请号：US11820303
申请日：2007-06-18
申请人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Oleg Gluschenkov , An Steegen , Haining Yang
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/02532 , H01L21/02636 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L27/1203 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
摘要翻译：提供了用于制造PFET和NFET的工艺。与栅堆叠相邻的第一半导体区域中的区域是凹进的。在凹槽中生长晶格不匹配的半导体层以向与其相邻的PFET的沟道区施加应变。可以在晶格失配的半导体层上生长第一半导体材料层，以及由硅层形成的硅化物以提供低电阻源极和漏极区域。

76. 发明授权

US07247546B2 Method of forming strained silicon materials with improved thermal conductivity 有权
标题翻译：形成具有改善导热性的应变硅材料的方法
公开(公告)号：US07247546B2
公开(公告)日：2007-07-24
申请号：US10710826
申请日：2004-08-05
申请人： Stephen W. Bedell , Huajie Chen , Keith Fogel , Ryan M. Mitchell , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Keith Fogel , Ryan M. Mitchell , Devendra K. Sadana
IPC分类号： H01L21/20 , H01L21/36 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

77. 发明授权

US07220626B2 Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels 失效
标题翻译：用于制造具有多个取向和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US07220626B2
公开(公告)日：2007-05-22
申请号：US10905978
申请日：2005-01-28
申请人： Huilong Zhu , Bruce B. Doris , Philip J. Oldiges , Meikei Ieong , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce B. Doris , Philip J. Oldiges , Meikei Ieong , Min Yang , Huajie Chen
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

78. 发明授权

US07169226B2 Defect reduction by oxidation of silicon 失效
标题翻译：通过氧化硅来减少缺陷
公开(公告)号：US07169226B2
公开(公告)日：2007-01-30
申请号：US10610612
申请日：2003-07-01
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B13/00 , H01L21/20
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.
摘要翻译：描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。这可以通过在高温下使用内部氧化来实现。以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

79. 发明申请

US20060027808A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 有权
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：US20060027808A1
公开(公告)日：2006-02-09
申请号：US10710826
申请日：2004-08-05
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Ryan Mitchell , Devendra Sadana
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer of Si or Ge is deposited on a substrate in a first depositing step; a second layer of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer having a plurality of Si layers and a plurality of Ge layers. The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer (so that a 1:1 ratio typically is realized with Si and Ge layers each about 10 Å thick). The combined SiGe layer is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer on the combined SiGe layer; the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中将第一层Si或Ge沉积在衬底上; 另一个元件的第二层在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层的组合SiGe层。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比（使得Si和Ge层的厚度通常为1：1，每个厚度大约为10埃）。组合的SiGe层的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合的SiGe层上沉积Si层的步骤; 组合的SiGe层被表征为弛豫的SiGe层，并且Si层是应变的Si层。对于SiGe层中更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

80. 发明申请

US20060011906A1 Ion implantation for suppression of defects in annealed SiGe layers 审中-公开
标题翻译：用于抑制退火SiGe层缺陷的离子注入
公开(公告)号：US20060011906A1
公开(公告)日：2006-01-19
申请号：US10890765
申请日：2004-07-14
申请人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
发明人： Stephen Bedell , Huajie Chen , Keith Fogel , Devendra Sadana , Ghavam Shahidi
IPC分类号： H01L29/06
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02532 , H01L21/02694 , H01L21/2658
摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed. The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.
摘要翻译：公开了一种用于制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si基材的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

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