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71. 发明申请

US20080136004A1 MULTI-CHIP PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：多芯片包装结构及其形成方法
公开(公告)号：US20080136004A1
公开(公告)日：2008-06-12
申请号：US11608404
申请日：2006-12-08
申请人： Wen-Kun Yang , Chun-Hui Yu , Chao-Nan Chou , Chih-Wei Lin , Ching-Shun Huang
发明人： Wen-Kun Yang , Chun-Hui Yu , Chao-Nan Chou , Chih-Wei Lin , Ching-Shun Huang
IPC分类号： H01L23/488 , H01L21/56
CPC分类号： H01L24/97 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16145 , H01L2224/24226 , H01L2224/24246 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/73209 , H01L2224/73267 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2224/83 , H01L2224/82 , H01L2224/81 , H01L2924/00012
摘要： To pick and place standard first chip size package on a base with a second chip for obtaining an appropriate stacking chip size package than the original chip size package. The package structure has a larger chip size package than the size of the traditional stacking package. Moreover, the terminal pins of the flip chip package may be located on peripheral of LGA package or on array of BGA package.
摘要翻译：在第二个芯片的基座上选择和放置标准的第一个芯片尺寸封装，以获得比原始芯片尺寸封装更适合的堆叠芯片尺寸封装。封装结构具有比传统堆叠封装尺寸更大的芯片尺寸封装。此外，倒装芯片封装的端子引脚可以位于LGA封装的外围或BGA封装的阵列上。

72. 发明申请

US20080085572A1 SEMICONDUCTOR PACKAGING METHOD BY USING LARGE PANEL SIZE 审中-公开
标题翻译：使用大面积尺寸的半导体封装方法
公开(公告)号：US20080085572A1
公开(公告)日：2008-04-10
申请号：US11538896
申请日：2006-10-05
申请人： Wen-Kun Yang , Chih-Wei Lin , Chun-Hui Yu
发明人： Wen-Kun Yang , Chih-Wei Lin , Chun-Hui Yu
IPC分类号： H01L21/60
CPC分类号： H01L21/6835 , H01L21/568 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L2221/68354 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/73267 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/09701
摘要： The present invention discloses a semiconductor packaging method, comprises steps of back lapping a processed silicon wafer to a desired thickness. Then, the dice are separated from the processed and lapped wafer into a single die. Then, the dice are picked and placed on a tool, an active surface of the dice is attached on the tool. A molding is performed to mold the dice by molding material. The tool is then removed from the dice to form a small unit. The next step is to arrange a plurality of the small units on a carrier in a matrix from. Then, a build-up layer, a re-distribution layer are formed over the dice, followed by forming solder balls on the dice. Finally, the carrier is removed.
摘要翻译：本发明公开了一种半导体封装方法，包括将经处理的硅晶片背面研磨成所需厚度的步骤。然后，将骰子从经处理和研磨的晶片分离成单个模具。然后，骰子被拾取并放置在工具上，骰子的活动表面附着在工具上。进行模制以通过模制材料模制骰子。然后将该工具从骰子中移除以形成小单元。下一步是将多个小单元布置在矩阵中的载体上。然后，在骰子上形成堆积层，再分布层，随后在骰子上形成焊球。最后，载体被移除。

73. 发明授权

US07338140B1 Computer housing 失效
标题翻译：电脑房
公开(公告)号：US07338140B1
公开(公告)日：2008-03-04
申请号：US11676295
申请日：2007-02-18
申请人： Yuh-Wen Huang , I-Ching Chou , Chun-Liang Li , Chih-Wei Lin
发明人： Yuh-Wen Huang , I-Ching Chou , Chun-Liang Li , Chih-Wei Lin
IPC分类号： A47B97/00
CPC分类号： G06F1/181 , H05K5/0239
摘要： A computer housing includes: a housing body having a front wall formed with a front opening and a mounting frame that defines a frame space and that has two opposite side walls, each of which is formed with two engaging holes and an engaging notch; and a faceplate having two engaging units, each of which includes a pair of first engaging arms and a second engaging arm. Each of the first engaging arms extends into a respective one of the engaging holes. The second engaging arm has a hook end in snap engagement with the engaging notch.
摘要翻译：计算机壳体包括：壳体，其具有形成有前开口的前壁和限定框架空间的安装框架，并且具有两个相对的侧壁，每个侧壁形成有两个接合孔和接合槽口; 以及具有两个接合单元的面板，每个接合单元包括一对第一接合臂和第二接合臂。每个第一接合臂延伸到相应的一个接合孔中。第二接合臂具有与接合凹口卡扣接合的钩端。

74. 发明授权

US08906599B2 Enhanced scanner throughput system and method 有权
标题翻译：增强扫描仪吞吐量系统和方法
公开(公告)号：US08906599B2
公开(公告)日：2014-12-09
申请号：US13473695
申请日：2012-05-17
申请人： Yu-Mei Liu , Chin-Hsiang Lin , Heng-Hsin Liu , Heng-Jen Lee , I-Hsiung Huang , Chih-Wei Lin
发明人： Yu-Mei Liu , Chin-Hsiang Lin , Heng-Hsin Liu , Heng-Jen Lee , I-Hsiung Huang , Chih-Wei Lin
IPC分类号： G03F7/20
CPC分类号： G03F7/70358
摘要： A method and system to improve scanner throughput is provided. An image from a reticle is projected onto a substrate using a continuous linear scanning procedure in which an entire column of die or cells of die is scanned continuously, i.e. without stepping to a different location. Each scan includes translating a substrate with respect to a fixed beam. While the substrate is translated, the reticle is also translated. When a first die or cell of die is projected onto the substrate, the reticle translates along a direction opposite the scan direction and as the scan continues along the same direction, the reticle then translates in the opposite direction of the substrate thereby forming an inverted pattern on the next die or cell. The time associated with exposing the substrate is minimized as the stepping operation only occurs after a complete column of cells is scanned.
摘要翻译：提供了一种提高扫描仪吞吐量的方法和系统。使用连续线性扫描程序将来自掩模版的图像投影到基板上，其中连续扫描整列管芯或裸片的单元，即不进入不同的位置。每个扫描包括相对于固定光束平移衬底。当底物被翻译时，掩模版也被翻译。当模具的第一裸片或裸片投影到衬底上时，标线沿着与扫描方向相反的方向平移，并且随着扫描沿着相同的方向继续，标线片然后沿着衬底的相反方向平移，从而形成倒置图案在下一个死亡或细胞。与曝光底物相关的时间最小化，因为步进操作仅在扫描完整的单元格列之后才发生。

75. 发明授权

US08837772B2 Image detecting method and system thereof 有权
标题翻译：图像检测方法及其系统
公开(公告)号：US08837772B2
公开(公告)日：2014-09-16
申请号：US12468224
申请日：2009-05-19
申请人： Tsann-Tay Tang , Chih-Wei Lin , Ming-Yu Shih
发明人： Tsann-Tay Tang , Chih-Wei Lin , Ming-Yu Shih
IPC分类号： G06K9/00
CPC分类号： G06K9/00771 , G06K9/4671
摘要： An image detecting method and a system thereof are provided. The image detecting method includes the following steps. An original image is captured. A moving-object image of the original image is created. An edge-straight-line image of the original image is created, wherein the edge-straight-line image comprises a plurality of edge-straight-lines. Whether the original image has a mechanical moving-object image is detected according to the length, the parallelism and the gap of the part of the edge-straight-lines corresponding to the moving-object image.
摘要翻译：提供了一种图像检测方法及其系统。图像检测方法包括以下步骤。捕获原始图像。创建原始图像的移动物体图像。创建原始图像的边缘直线图像，其中边缘直线图像包括多条边缘直线。根据对应于移动物体图像的边缘直线的一部分的长度，平行度和间隙来检测原始图像是否具有机械移动物体图像。

76. 发明申请

US20080166055A1 Symbol Recognition Method 有权
标题翻译：符号识别方法
公开(公告)号：US20080166055A1
公开(公告)日：2008-07-10
申请号：US11846628
申请日：2007-08-29
申请人： Ming-Hung Lin , Chih-Wei Lin
发明人： Ming-Hung Lin , Chih-Wei Lin
IPC分类号： G06K9/18
CPC分类号： G06K9/2054 , G06K2209/01
摘要： A symbol recognition method for increasing the symbol recognition speed by the processor includes the steps of obtaining a pixel density value and an aspect ratio of the symbol image. Then, the center-point value and the corresponding radius value are obtained by a partitional clustering algorithm. In sequence, a pixel density value and the aspect ratio of the under recognized image are obtained, and compared with the values of the symbol image to determine whether the under recognized image is a single symbol image or not.
摘要翻译：用于通过处理器增加符号识别速度的符号识别方法包括以下步骤：获得符号图像的像素密度值和宽高比。然后，通过分数聚类算法获得中心点值和对应的半径值。顺序地，获得像素密度值和未识别图像的纵横比，并且与符号图像的值进行比较，以确定未识别的图像是否是单个符号图像。

77. 发明申请

US20070027567A1 Methods for optimizing die placement 有权
标题翻译：优化模具放置的方法
公开(公告)号：US20070027567A1
公开(公告)日：2007-02-01
申请号：US11222374
申请日：2005-09-08
申请人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
发明人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G03F7/70433 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
摘要翻译：在具有计算系统的对准标记的晶片上优化管芯放置的方法包括在第一位置上在晶片上布置多个场。傻瓜插入在至少一个布置的场和对准标记之间并且相邻于晶片边缘插入。确定在第一位置在晶片上可制造的模具的总数。晶片位置相对于多个场的位置移动到第二位置，并且确定在第二位置处在晶片上可制造的模具的总数。比较了从第一和第二位置中的每一个的可制造模具的总数，并且具有较高数量的可制造模具的位置是最佳模具放置位置的候选者。然后评估总场数，虚拟人总数以及共享虚拟人总数，以确定最佳管桩位置。

78. 发明授权

US09284424B2 Polyimide film and fabrication method thereof 有权
标题翻译：聚酰亚胺膜及其制造方法
公开(公告)号：US09284424B2
公开(公告)日：2016-03-15
申请号：US14249702
申请日：2014-04-10
申请人： Chih-Wei Lin , Meng-Ying Tsai
发明人： Chih-Wei Lin , Meng-Ying Tsai
IPC分类号： B32B5/16 , C08G73/10 , C08J5/18 , C08L79/08 , B29C39/00 , C09D179/08 , B29K79/00 , B29K105/00
CPC分类号： C08J5/18 , B29C39/003 , B29K2079/08 , B29K2105/0032 , C08G73/1067 , C08G73/1071 , C08J2379/08 , C09D179/08
摘要： A polyimide film includes a polyimide polymer forming a main molecular structure of the polyimide film, and polyimide particles present in the polyimide film at a weight ratio between about 15 wt % and 30 wt % of a total weight of the polyimide film, the polyimide particles having an average diameter between about 3 μm and 8 μm. The polyimide film can have a 60° gloss value equal to or smaller than 10, a haze equal to or higher than 90%, and a Young's modulus equal to or higher than 280 kgf/mm2. In some embodiments, methods of fabricating the polyimide film are also described.
摘要翻译：聚酰亚胺膜包括形成聚酰亚胺膜的主要分子结构的聚酰亚胺聚合物和以聚酰亚胺膜的总重量的约15重量％至30重量％的重量比存在于聚酰亚胺膜中的聚酰亚胺颗粒，聚酰亚胺颗粒平均直径约3μm至8μm。聚酰亚胺膜可以具有等于或小于10的60°光泽值，雾度等于或高于90％，杨氏模量等于或高于280kgf / mm2。在一些实施例中，还描述了制造聚酰亚胺膜的方法。

79. 发明授权

US08605235B2 Display device and method of measuring surface structure thereof 有权
标题翻译：显示装置及其表面结构的测量方法
公开(公告)号：US08605235B2
公开(公告)日：2013-12-10
申请号：US12779915
申请日：2010-05-13
申请人： Chih-Wei Lin , Min-Cheng Wang , Yung-Cheng Chen , Hung-Min Liu
发明人： Chih-Wei Lin , Min-Cheng Wang , Yung-Cheng Chen , Hung-Min Liu
IPC分类号： G02F1/1335
CPC分类号： G01B11/24 , G01B5/061 , G01B11/00 , G01B11/02 , G01B11/0608 , G01B11/08 , G01B17/02 , G02F1/133512 , G02F1/13394 , G03F7/70625
摘要： A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings.
摘要翻译：提供显示装置和测量其表面结构的方法。显示装置包括第一和第二基板，第一和第二图案化遮光层以及第一和第二像素单元。设置在第一基板的表面上的第一图案化遮光层包括第一开口。设置在第一图案化遮光层中的第一基板的表面上的第二图案遮光层包括第二开口。第一像素单元包括第一和第二突起。第一突起相应地覆盖第一开口和第一图案化遮光层的一部分。第二突起设置在第一和第二图案化的遮光层中。第二像素单元包括对应地覆盖第二开口的第三突起和第二图案化遮光层的一部分，其中第二开口的尺寸小于第一开口的尺寸。

80. 发明授权

US08239788B2 Frame cell for shot layout flexibility 有权
标题翻译：帧单元，用于拍摄布局灵活性
公开(公告)号：US08239788B2
公开(公告)日：2012-08-07
申请号：US12537836
申请日：2009-08-07
申请人： Chih-Wei Lin , Yung-Cheng Chen , Heng-Jen Lee
发明人： Chih-Wei Lin , Yung-Cheng Chen , Heng-Jen Lee
IPC分类号： G06F17/50 , G03C5/00
CPC分类号： G03F7/70433
摘要： A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count.
摘要翻译：一种方法包括接收集成电路芯片尺寸并基于芯片尺寸确定帧结构段大小。帧结构段大小小于芯片大小。建立具有芯片数量的初始照片布局，其中每个包括至少一个框架结构段和至少一个芯片的镜头排列在垂直和水平排列的列和行中。建立至少一个额外的镜头布局，其中一列或一列镜头中的至少一个从相邻的行或镜头列偏移。将初始照片布局与至少一个附加镜头布局进行比较，并且部分地基于镜头布局中的总镜头数量选择最终镜头布局，并且具有大于或等于初始镜头布局的最终裁片数量芯片数量

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