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1. 发明授权

US07353077B2 Methods for optimizing die placement 有权
标题翻译：优化模具放置的方法
公开(公告)号：US07353077B2
公开(公告)日：2008-04-01
申请号：US11222374
申请日：2005-09-08
申请人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
发明人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
IPC分类号： G06F19/00
CPC分类号： G03F7/70433 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
摘要翻译：在具有计算系统的对准标记的晶片上优化管芯放置的方法包括在第一位置上在晶片上布置多个场。傻瓜插入在至少一个布置的场和对准标记之间并且相邻于晶片边缘插入。确定在第一位置在晶片上可制造的模具的总数。晶片位置相对于多个场的位置移动到第二位置，并且确定在第二位置处在晶片上可制造的模具的总数。比较了从第一和第二位置中的每一个的可制造模具的总数，并且具有较高数量的可制造模具的位置是最佳模具放置位置的候选者。然后评估总场数，虚拟人总数以及共享虚拟人总数，以确定最佳管桩位置。

2. 发明申请

US20070027567A1 Methods for optimizing die placement 有权
标题翻译：优化模具放置的方法
公开(公告)号：US20070027567A1
公开(公告)日：2007-02-01
申请号：US11222374
申请日：2005-09-08
申请人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
发明人： Chih-Wei Lin , Hong-Hsing Chou , Yeh-Jye Wang , Chen-Fu Chien , Jen-Hsin Wang , Chih-Wei Hsiao
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G03F7/70433 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing die placement on a wafer having an alignment mark with a computing system includes arranging a plurality of fields on the wafer in a first position. Dummies are inserted between at least one arranged field and the alignment mark and inserted adjacent to the wafer edge. The total number of dies manufacturable on the wafer at the first position is determined. The wafer position is shifted to a second position relative to the position of the plurality of fields, and the total number of dies manufacturable on the wafer at the second position is determined. The total number of manufacturable dies from each of the first and the second positions is compared, and the positions having the higher number of manufacturable die are candidates of optimal die placement position. Then the total number of fields, the total number of dummies, and the total number of shared dummies are evaluated to decide the optimal die placement position.
摘要翻译：在具有计算系统的对准标记的晶片上优化管芯放置的方法包括在第一位置上在晶片上布置多个场。傻瓜插入在至少一个布置的场和对准标记之间并且相邻于晶片边缘插入。确定在第一位置在晶片上可制造的模具的总数。晶片位置相对于多个场的位置移动到第二位置，并且确定在第二位置处在晶片上可制造的模具的总数。比较了从第一和第二位置中的每一个的可制造模具的总数，并且具有较高数量的可制造模具的位置是最佳模具放置位置的候选者。然后评估总场数，虚拟人总数以及共享虚拟人总数，以确定最佳管桩位置。

3. 发明授权

US07586609B2 Method for analyzing overlay errors 有权
标题翻译：分析重叠错误的方法
公开(公告)号：US07586609B2
公开(公告)日：2009-09-08
申请号：US11112115
申请日：2005-04-21
申请人： Shun-Li Lin , Chen-Fu Chien , Chia-Yu Hsu , I-Pien Wu
发明人： Shun-Li Lin , Chen-Fu Chien , Chia-Yu Hsu , I-Pien Wu
IPC分类号： G01B11/00
CPC分类号： G03F7/70633 , G03F7/705
摘要： A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.
摘要翻译：描述了用于分析光刻中的重叠误差的方法。首先进行场间采样和场内采样，以对每个晶片上的多个位置进行采样，然后测量每个位置处的重叠误差值。使用包括不同类型的场内和场间覆盖误差系数的重叠误差模型来拟合相对于采样位置的测量重叠误差值。在叠加误差模型中，场内重叠误差包括场内平移，各向同性放大，标线旋转，不对称放大和不对称旋转，场间叠加误差包括场间平移，尺度误差，晶圆旋转和正交误差。

4. 发明授权

US06368761B1 Procedure of alignment for optimal wafer exposure pattern 有权
标题翻译：对准最佳晶片曝光图案的步骤
公开(公告)号：US06368761B1
公开(公告)日：2002-04-09
申请号：US09568323
申请日：2000-05-09
申请人： Chen-Fu Chien , Shao-Chung Hsu , Chih-Ping Chen
发明人： Chen-Fu Chien , Shao-Chung Hsu , Chih-Ping Chen
IPC分类号： G03F900
CPC分类号： G03F9/7084 , G03F7/70433 , G03F9/7046
摘要： Conventionally, efforts to improve the yield of chips produced on a wafer focused on defect reduction. Another approach is optimizing wafer exposure patterns. The present invention includes a computer-based procedure and apparatus to expose cells on the surface of a wafer so as to maximize the number of dies produced from a wafer. The invention is useful in the exposure of six and eight inch wafers, as well as larger wafers.
摘要翻译：通常，提高晶片上产生的芯片的产量的努力集中在缺陷减少。另一种方法是优化晶片曝光模式。本发明包括一种基于计算机的程序和装置，用于暴露晶片表面上的单元，从而最大化从晶片产生的模具的数量。本发明可用于六和八英寸晶片以及较大晶片的曝光。

5. 发明授权

US06975974B2 Overlay error model, sampling strategy and associated equipment for implementation 有权
标题翻译：覆盖误差模型，采样策略和相关设备实施
公开(公告)号：US06975974B2
公开(公告)日：2005-12-13
申请号：US09920034
申请日：2001-08-01
申请人： Chen-Fu Chien , Kuo-Hao Chang , Chih-Ping Chen , Shun-Li Lin
发明人： Chen-Fu Chien , Kuo-Hao Chang , Chih-Ping Chen , Shun-Li Lin
IPC分类号： G03F7/20 , H01L21/66 , G06F17/10
CPC分类号： G03F7/705 , G03F7/70533 , G03F7/70633 , H01L22/20
摘要： In the manufacturing of VLSI circuits, production of overlay is a critical step. To obtain a higher resolution and alignment accuracy in microlithographic process, overlay errors must be measured so that overlay errors can be reduced to a tolerable level. This invention provides an overlay error model and a sampling strategy. Utilizing the overlay model and sampling strategy, a device for measuring overlay errors is also designed.
摘要翻译：在VLSI电路的制造中，覆盖层的生产是关键的一步。为了在微光刻工艺中获得更高的分辨率和对准精度，必须测量重叠误差，以便覆盖误差可以降低到可容忍的水平。本发明提供了重叠误差模型和采样策略。利用覆盖模型和采样策略，还设计了测量重叠误差的装置。

6. 发明申请

US20060238761A1 Method for analyzing overlay errors 有权
公开(公告)号：US20060238761A1
公开(公告)日：2006-10-26
申请号：US11112115
申请日：2005-04-21
申请人： Shun-Li Lin , Chen-Fu Chien , Chia-Yu Hsu , I-Pien Wu
发明人： Shun-Li Lin , Chen-Fu Chien , Chia-Yu Hsu , I-Pien Wu
IPC分类号： G01B11/00
CPC分类号： G03F7/70633 , G03F7/705
摘要： A method for analyzing overlay errors in lithography is described. Interfield sampling and intrafield sampling are first conducted to sample multiple positions on each of the wafers, and then the overlay error value at each of the positions is measured. An overlay error model including coefficients of intrafield and interfield overlay errors of different types is used to fit the measured overlay error values with respect to the sampled positions. In the overlay error model, the intrafield overlay errors include intrafield translation, isotropic magnification, reticle rotation, asymmetric magnification and asymmetric rotation, and the interfield overlay errors include interfield translation, scale error, wafer rotation and orthogonality error.

7. 发明申请

US20050003617A1 Template padding method for padding edges of holes on semiconductor masks 审中-公开
标题翻译：用于在半导体掩模上填充孔的边缘的模板填充方法
公开(公告)号：US20050003617A1
公开(公告)日：2005-01-06
申请号：US10613817
申请日：2003-07-01
申请人： Shun-Li Lin , Chen-Fu Chien , Jing-Feng Deng
发明人： Shun-Li Lin , Chen-Fu Chien , Jing-Feng Deng
IPC分类号： G03F1/14 , G03F7/00 , H01L21/027 , H01L21/8234 , H01L21/8246 , H01L21/8247 , H01L27/112
CPC分类号： G03F1/36 , H01L27/112 , H01L27/11253
摘要： A template padding method for padding edges of at least one hole on a semiconductor mask. The exposure and padding process is modulized. A padding database is developed based on the feature size and the pattern to be exposed. In the method of the present invention, the environment to be exposed is found firstly, and specific exposure module is then searched out. The padding result of the module is pre-found and stored in a database by diffraction operation, such as OPC method. Padding of a hole on a mask about a cell of a wafer can be performed directly by using a value stored. The complicated calculation can be greatly reduced. The method is adjustable according to the feature size of the product and the exposing pattern. The method can be used to random-distribution of holes on a mask surface, so as to determine a padding area effectively.
摘要翻译：一种用于在半导体掩模上填充至少一个孔的边缘的模板填充方法。暴露和填充过程被模拟。基于要暴露的特征尺寸和图案开发填充数据库。在本发明的方法中，首先找到要暴露的环境，然后搜索特定的曝光模块。模块的填充结果通过诸如OPC方法的衍射操作预先发现并存储在数据库中。可以通过使用存储的值来直接执行在晶片的单元周围的掩模上的孔的填充。复杂的计算可以大大减少。该方法根据产品的特征尺寸和曝光图案可调。该方法可以用于掩模表面上的空穴的随机分布，从而有效地确定填充区域。

8. 发明授权

US08407631B2 Method for enhancing wafer exposure effectiveness and efficiency 有权
标题翻译：提高晶圆曝光效率和效率的方法
公开(公告)号：US08407631B2
公开(公告)日：2013-03-26
申请号：US12860572
申请日：2010-08-20
申请人： Chen-Fu Chien , Chia-Yu Hsu
发明人： Chen-Fu Chien , Chia-Yu Hsu
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： The present invention applies the data mining methodology by which the wafer exposure effectiveness and efficiency are predictable in terms of the chip size, chip length and chip width. More specifically, in the present invention, an index, named “Mask-field-utilization weighted Overall Wafer Effectiveness” (MOWE), integrates the two parameters of “Overall Wafer Effectiveness” (OWE) and “Mask-Field-Utilization” (MFU), mainly regarding the wafer exposure effectiveness and efficiency respectively, in order to construct a model tree of the MOWE to achieve the data mining. By the MOWE model tree, the causal relationship between design independent variables and fabrication dependent variables is constructed, which can be accordingly applied as design guidelines in the design phase to improve the chip layout in order to produce a better wafer exposure effectiveness and efficiency.
摘要翻译：本发明应用数据挖掘方法，根据芯片尺寸，芯片长度和芯片宽度可以预测晶片曝光效率和效率。更具体地说，在本发明中，称为掩模场利用加权的总体晶片有效性（MOWE）的指数集成了主要关于晶片的总体晶片效率（OWE）和掩模场利用率（MFU）的两个参数暴露效果和效率分别为了构建MOWE的模型树来实现数据挖掘。通过MOWE模型树，构建了设计独立变量与制造因变量之间的因果关系，可以在设计阶段作为设计指南应用，以提高芯片布局，从而产生更好的晶片曝光效率和效率。

9. 发明授权

US08200528B2 Factor analysis system and analysis method thereof 有权
标题翻译：因子分析系统及其分析方法
公开(公告)号：US08200528B2
公开(公告)日：2012-06-12
申请号：US12907237
申请日：2010-10-19
申请人： Chen-Fu Chien , Chih-Han Hu
发明人： Chen-Fu Chien , Chih-Han Hu
IPC分类号： G06Q10/00
CPC分类号： G06F17/18 , G06Q10/06 , G06Q10/063 , G06Q10/0635 , G06Q10/06375 , G06Q10/0639 , G06Q10/06393 , G06Q10/06395
摘要： A factor analysis system and method thereof is disclosed. The factor analysis system comprises a data receiving module for receiving a plurality of factors having influence on a target total value, a plurality of base values corresponding to the factors, and a target improvement percentage; a first computing unit for computing a reference target total value and a plurality of upgraded target total values; a second computing unit using the upgraded target total values and the reference target total value to compute the sensitivity of each of the factors; and a processing module for multiplying a factor improvement of each factor in percentage point by the factor sensitivity of each factor to obtain the level of contribution of each factor to the target total value. Through the factor analysis, a decision maker can decide the optimal combination of different factor improvements for achieving the planned target total value.
摘要翻译：公开了一个因素分析系统及其方法。因子分析系统包括数据接收模块，用于接收对目标总值有影响的多个因素，对应于因素的多个基本值和目标改进百分比; 用于计算参考目标总值和多个升级目标总值的第一计算单元; 使用升级的目标总值和参考目标总值的第二计算单元来计算每个因素的敏感度; 以及用于将每个因子的因子改善乘以每个因子的因子灵敏度的处理模块，以获得每个因子对目标总值的贡献水平。通过因子分析，决策者可以决定不同因素改进的最佳组合来实现计划目标总价值。

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