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71. 发明申请

US20100046300A1 REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE 有权
标题翻译：减少存储器件中的快速充电损失
公开(公告)号：US20100046300A1
公开(公告)日：2010-02-25
申请号：US12195552
申请日：2008-08-21
申请人： Vishal Sarin , William Saiki , Frankie F. Roohparvar
发明人： Vishal Sarin , William Saiki , Frankie F. Roohparvar
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
摘要翻译：公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。在负脉冲之后，执行程序验证操作。

72. 发明申请

US20090310407A1 SENSING AGAINST A REFERENCE CELL 有权
标题翻译：感染参考细胞
公开(公告)号：US20090310407A1
公开(公告)日：2009-12-17
申请号：US12137988
申请日：2008-06-12
申请人： Frankie F. Roohparvar , Vishal Sarin
发明人： Frankie F. Roohparvar , Vishal Sarin
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C16/28
摘要： Memory devices, bulk storage devices, and methods of operating memory are disclosed, such as those adapted to process and generate analog data signals representative of data values of two or more bits of information. Programming of such memory devices can include programming to a target threshold voltage within a range representative of the desired bit pattern. Reading such memory devices can include generating an analog data signal indicative of a threshold voltage of a target memory cell. The target memory cell can be sensed against a reference cell includes a dummy string of memory cells connected to a target string of memory cells, and, such as by using a differential amplifier to sense a difference between a reference cell and the target cell. This may allow a wider range of voltages to be used for data states.
摘要翻译：公开了存储器件，大容量存储器件和操作存储器的方法，诸如适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的那些。这种存储器件的编程可以包括在表示期望的位模式的范围内对目标阈值电压进行编程。读取这样的存储器件可以包括产生指示目标存储器单元的阈值电压的模拟数据信号。可以相对于参考单元感测目标存储器单元，包括连接到存储器单元的目标串的存储器单元的虚拟串，并且例如通过使用差分放大器来感测参考单元和目标单元之间的差异。这可能允许更广泛的电压范围用于数据状态。

73. 发明申请

US20090097311A1 NON-EQUAL THRESHOLD VOLTAGE RANGES IN MLC NAND 有权
标题翻译： MLC NAND中的非均衡阈值电压范围
公开(公告)号：US20090097311A1
公开(公告)日：2009-04-16
申请号：US11869868
申请日：2007-10-10
申请人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung-Sheng Hoei
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C27/005
摘要： Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data transfer rates relative to devices processing and generating only binary data signals indicative of individual bits. Programming of such memory devices includes programming to a target threshold voltage range representative of the desired bit pattern. Reading such memory devices includes generating an analog data signal indicative of a threshold voltage of a target memory cell. Threshold voltage ranges of the memory cells have a larger range size for ranges that include lower threshold voltages and a smaller range size for ranges that include higher threshold voltages since program disturb is lower at higher threshold voltages.
摘要翻译：适于处理和产生表示两个或更多位信息的数据值的模拟数据信号的存储器件有助于相对于器件处理和仅产生指示各个位的二进制数据信号的数据传输速率的增加。这种存储器件的编程包括编程到表示所需位图案的目标阈值电压范围。读取这样的存储器件包括产生指示目标存储器单元的阈值电压的模拟数据信号。存储器单元的阈值电压范围对于包括较低阈值电压的范围具有较大的范围尺寸，并且对于包括较高阈值电压的范围的较小范围尺寸，因为在较高阈值电压下编程干扰较低。

74. 发明申请

US20090021987A1 Analog sensing of memory cells in a solid state memory device 有权
标题翻译：模拟感测固态存储器件中的存储单元
公开(公告)号：US20090021987A1
公开(公告)日：2009-01-22
申请号：US11879907
申请日：2007-07-19
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C27/005 , G11C27/02 , G11C2211/5621 , G11C2211/5634
摘要： A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.
摘要翻译：一种存储器件，其包括耦合到位线的采样和保持电路。采样和保持电路存储所选存储单元的目标阈值电压。存储单元被编程，然后用斜坡读取电压进行验证。将存储单元接通的读取电压存储在采样和保持电路中。将目标阈值电压与比较器电路的读取电压进行比较。当读取电压至少基本上等于（即，基本上等于和/或开始超过）目标阈值电压时，比较器电路产生禁止信号。

75. 发明申请

US20080273384A1 Non-volatile multilevel memory cells with data read of reference cells 有权
标题翻译：具有参考单元数据读取的非易失性多电平存储单元
公开(公告)号：US20080273384A1
公开(公告)日：2008-11-06
申请号：US11799658
申请日：2007-05-02
申请人： Vishal Sarin , Jung Sheng Hoei , Frankie F. Roohpavar
发明人： Vishal Sarin , Jung Sheng Hoei , Frankie F. Roohpavar
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.
摘要翻译：本公开的实施例提供用于参考单元的数据读取的用于非易失性多级存储器单元数据检索的方法，设备，模块和系统。一种方法包括将耦合到所选字线的多个数据单元的至少一个数据单元编程为对应于目标状态的目标数据阈值电压（Vt）电平; 将耦合到所选字线的多个参考单元的至少一个参考单元编程为目标参考Vt电平，与数据单元数量交织的参考单元的数量; 基于所述至少一个参考单元的数据读取确定参考状态; 以及基于所述至少一个参考单元的改变来改变从所述至少一个数据单元读取的状态。

76. 发明授权

US07336516B2 Unified multilevel memory systems and methods 有权
标题翻译：统一的多级内存系统和方法
公开(公告)号：US07336516B2
公开(公告)日：2008-02-26
申请号：US11229191
申请日：2005-09-15
申请人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

77. 发明授权

US07161844B2 Method and apparatus for compensating for bitline leakage current 有权
标题翻译：用于补偿位线泄漏电流的方法和装置
公开(公告)号：US07161844B2
公开(公告)日：2007-01-09
申请号：US10814443
申请日：2004-03-30
申请人： Vishal Sarin , Hieu Van Tran , Dana Lee
发明人： Vishal Sarin , Hieu Van Tran , Dana Lee
IPC分类号： G11C7/10
CPC分类号： G11C16/0433 , G11C7/12 , G11C16/10
摘要： A bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.
摘要翻译：一种位线泄漏电流补偿电路，用于通过测量非操作存储器阵列或虚拟存储器阵列中的漏电流并向电流源提供反馈信号或提供补偿电流来补偿操作存储器阵列中的漏电流。

78. 发明授权

US06992934B1 Read bitline inhibit method and apparatus for voltage mode sensing 有权
标题翻译：读取位线抑制方法和电压模式检测装置
公开(公告)号：US06992934B1
公开(公告)日：2006-01-31
申请号：US11080595
申请日：2005-03-15
申请人： Vishal Sarin , Hieu Van Tran , Jack Frayer
发明人： Vishal Sarin , Hieu Van Tran , Jack Frayer
IPC分类号： G11C16/08
CPC分类号： G11C11/5642
摘要： A multilevel memory system uses a source line driver circuit and a read bitline inhibit driver circuit to eliminate inhibit offset currents on unselected bitlines before memory operations of selected memory cells to equalize voltages before the operation.
摘要翻译：多电平存储器系统使用源极线驱动电路和读位线禁止驱动器电路来消除在所选择的存储器单元的存储器操作之前对未选位线的禁止偏移电流，以在操作之前对电压进行均衡。

79. 发明授权

US06748484B1 Match resolution circuit for an associative memory 失效
标题翻译：匹配分辨率电路用于关联存储器
公开(公告)号：US06748484B1
公开(公告)日：2004-06-08
申请号：US09637131
申请日：2000-08-10
申请人： Alex E. Henderson , Walter E. Croft , Raymond M. Chu , Vishal Sarin
发明人： Alex E. Henderson , Walter E. Croft , Raymond M. Chu , Vishal Sarin
IPC分类号： G06F1200
CPC分类号： G11C15/00 , G11C15/04
摘要： A system and method for determining a best match from a plurality of matches received in response to a search input for an associative memory includes a priority field associated with each data item stored in the associative memory. The priority field corresponds to criteria that is used to order the priority of the data items in the associative memory. A match resolution circuit is coupled to receive match signals from an associative memory, such as a CAM, and the priority fields of the matching data items. The match resolution structure compares the priority fields of the matching data items to determine which data item has the highest priority. The match resolution structure indicates the data item with the highest priority in the priority field as the best match of the associative memory for the particular search input.
摘要翻译：用于响应于关联存储器的搜索输入而接收的多个匹配来确定最佳匹配的系统和方法包括与存储在关联存储器中的每个数据项相关联的优先级字段。优先级字段对应于用于对关联存储器中的数据项的优先级进行排序的标准。匹配分辨率电路被耦合以从诸如CAM的关联存储器和匹配数据项的优先级字段接收匹配信号。匹配分辨率结构比较匹配数据项的优先级字段以确定哪个数据项具有最高优先级。匹配分辨率结构指示优先级字段中具有最高优先级的数据项作为特定搜索输入的关联存储器的最佳匹配。

80. 发明授权

US6081603A Method and apparatus for automatic gain control using a linear limiter circuit with voltage controlled resistors as a variable element 失效
标题翻译：使用具有压控电阻器作为可变元件的线性限幅器电路进行自动增益控制的方法和装置
公开(公告)号：US6081603A
公开(公告)日：2000-06-27
申请号：US925022
申请日：1997-09-08
申请人： Lawrence D. Engh , Jung Sheng Hoei , Vishal Sarin
发明人： Lawrence D. Engh , Jung Sheng Hoei , Vishal Sarin
IPC分类号： H03G3/12 , H03G1/00 , H03G3/30 , H03F21/00
CPC分类号： H03G3/3005 , H03G1/007
摘要： The present invention relates to a method and apparatus for adjusting the gain of an amplifier circuit. A gain control circuit compares the output of the amplifier with a reference voltage and adjusts a variable resistor, thereby altering the gain of the amplifier.
摘要翻译：本发明涉及一种用于调整放大器电路的增益的方法和装置。增益控制电路将放大器的输出与参考电压进行比较，并调整可变电阻，从而改变放大器的增益。

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