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71. 发明申请

US20060054934A1 Using oxynitride spacer to reduce parasitic capacitance in CMOS devices 有权
标题翻译：使用氮氧化物间隔物来减少CMOS器件中的寄生电容
公开(公告)号：US20060054934A1
公开(公告)日：2006-03-16
申请号：US10938179
申请日：2004-09-11
申请人： Yuanning Chen , Haowen Bu , Kaiping Liu
发明人： Yuanning Chen , Haowen Bu , Kaiping Liu
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： H01L29/6656 , H01L21/823864 , H01L29/66598 , H01L29/7833
摘要： A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate 100, forming a gate structure 108 over the substrate, depositing a first layer 104 atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiOxNyCz) layer 250 atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer 112 atop the oxynitride layer, and depositing a nitride layer 114B atop the second layer.
摘要翻译：互补金属氧化物半导体（CMOS）器件具有衬底100，设置在衬底顶部的栅极结构108和沉积在栅极结构108的相对侧上的间隔物250，以控制衬底中的深源极漏极区S，D的形成。间隔物250由氧氮化物（SiO x N y O z C z z）形成，其中x和y不为零，但z可以为零或更大这种氧氮化物间隔物减少寄生电容，从而提高器件性能。制造互补金属氧化物半导体（CMOS）器件的一部分的方法包括提供衬底100，在衬底上形成栅极结构108，在栅极结构的相对侧上沉积衬底顶部的第一层104，以形成在衬底中的深源极漏极区域，在第一层的顶部上沉积氧氮化物（SiO x N x N z C z z）层250（其中x 并且y不为零但z可以为零或更大），在氧氮化物层的顶部沉积第二层112，以及在第二层顶上沉积氮化物层114B。

72. 发明申请

US20060024873A1 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US20060024873A1
公开(公告)日：2006-02-02
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

73. 发明申请

US20050215055A1 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor 有权
标题翻译：具有全硅化物栅电极的半导体器件及其制造方法
公开(公告)号：US20050215055A1
公开(公告)日：2005-09-29
申请号：US10808168
申请日：2004-03-24
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

74. 发明申请

US20050133876A1 Reduced hydrogen sidewall spacer oxide 有权
公开(公告)号：US20050133876A1
公开(公告)日：2005-06-23
申请号：US10739973
申请日：2003-12-17
申请人： Haowen Bu , Clinton Montgomery , Amitabh Jain
发明人： Haowen Bu , Clinton Montgomery , Amitabh Jain
IPC分类号： H01L21/314 , H01L21/316 , H01L21/336 , H01L21/338 , H01L29/49 , H01L29/76 , H01L29/78 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02362 , H01L21/3145 , H01L21/31612 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

75. 发明申请

US20050133835A1 Reduced hydrogen sidewall spacer oxide 有权
标题翻译：还原氢侧壁间隔氧化物
公开(公告)号：US20050133835A1
公开(公告)日：2005-06-23
申请号：US10959689
申请日：2004-10-06
申请人： Haowen Bu , Clinton Montgomery , Amitabh Jain
发明人： Haowen Bu , Clinton Montgomery , Amitabh Jain
IPC分类号： H01L21/314 , H01L21/316 , H01L21/336 , H01L21/338 , H01L29/49 , H01L29/76 , H01L29/78 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02362 , H01L21/3145 , H01L21/31612 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.
摘要翻译：本发明的一个实施例是制造半导体结构10的方法，其中通过无氢前体CVD工艺形成间隔氧化物层90。本发明的另一实施例是具有氢含量小于1％的间隔氧化物层90的半导体结构10。

76. 发明申请

US20050118770A1 Method for introducing hydrogen into a channel region of a metal oxide semiconductor (MOS) device 审中-公开
标题翻译：将氢引入金属氧化物半导体（MOS）器件的沟道区域的方法
公开(公告)号：US20050118770A1
公开(公告)日：2005-06-02
申请号：US10956864
申请日：2004-10-01
申请人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
发明人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
IPC分类号： H01L21/30 , H01L21/324 , H01L21/336 , H01L29/78 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/3003 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain regions in the substrate (210). The method further includes annealing the substrate containing the at least a portion of source/drain regions in the presence of hydrogen, and forming an interlevel dielectric layer over the substrate (210) having previously been annealed in the presence of hydrogen.
摘要翻译：本发明提供一种半导体器件的制造方法及其制造方法。除了其他步骤之外，制造半导体器件的方法包括在衬底（210）上形成栅极结构（230）并且形成衬底（210）中的源极/漏极区域的至少一部分。该方法还包括在存在氢的情况下对包含至少一部分源极/漏极区的衬底进行退火，以及在预先在氢气存在下预先退火的衬底（210）上形成层间电介质层。

77. 发明申请

US20110120374A1 System and Method for Mitigating Oxide Growth in a Gate Dielectric 审中-公开
标题翻译：降低栅极电介质中氧化物生长的系统和方法
公开(公告)号：US20110120374A1
公开(公告)日：2011-05-26
申请号：US13017828
申请日：2011-01-31
申请人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
发明人： Malcolm J. Bevan , Haowen Bu , Hiroaki Niimi , Husam N. Alshareef
IPC分类号： H01L21/469
CPC分类号： H01L21/28158 , C23C16/45557 , C23C16/4582 , H01J37/32752 , H01J37/32825 , H01J37/32899 , H01J2237/3321 , H01L21/02181 , H01L21/0223 , H01L21/02255 , H01L21/02318 , H01L21/02323 , H01L21/02326 , H01L21/02329 , H01L21/02332 , H01L21/0234 , H01L21/28035 , H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3105 , H01L21/31604 , H01L21/318 , H01L21/3205 , H01L21/324 , H01L21/67161 , H01L21/67167 , H01L21/67196 , H01L21/67201 , H01L21/6776 , H01L29/42364 , H01L29/4908 , H01L29/4916 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78
摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
摘要翻译：可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

78. 发明授权

US07795122B2 Antimony ion implantation for semiconductor components 有权
标题翻译：半导体元件的锑离子注入
公开(公告)号：US07795122B2
公开(公告)日：2010-09-14
申请号：US11725927
申请日：2007-03-20
申请人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
发明人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译：公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

79. 发明申请

US20090004853A1 METHOD FOR FORMING A METAL SILICIDE 有权
标题翻译：形成金属硅化物的方法
公开(公告)号：US20090004853A1
公开(公告)日：2009-01-01
申请号：US11770593
申请日：2007-06-28
申请人： Haowen Bu , Shashank Ekbote , Juanita Deloach
发明人： Haowen Bu , Shashank Ekbote , Juanita Deloach
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.
摘要翻译：本申请涉及形成金属硅化物层的方法。该方法包括提供包括硅的衬底并在衬底上沉积金属层。金属层在第一温度范围内退火，并且在约10毫秒或更短的第一停留时间内使至少一部分金属与硅反应形成硅化物。将金属的未反应部分从基材上除去。硅化物在第二温度范围内退火约10毫秒或更短的第二停留时间。

80. 发明授权

US07429517B2 CMOS transistor using high stress liner layer 有权
标题翻译： CMOS晶体管采用高应力衬层
公开(公告)号：US07429517B2
公开(公告)日：2008-09-30
申请号：US10845456
申请日：2004-05-13
申请人： Zhiqiang Wu , Haowen Bu
发明人： Zhiqiang Wu , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L29/6659 , H01L29/7843
摘要： A MOS transistor structure comprising a gate dielectric layer (30), a gate electrode (40), and source and drain regions (70) are formed in a semiconductor substrate (10). First second and third dielectric layers (110), (120), and (130) are formed over the MOS transistor structure. The second and third dielectric structures (120), (130) are removed leaving a MOS transistor with a stressed channel region resulting in improved channel mobility characteristics.
摘要翻译：在半导体衬底（10）中形成包括栅极电介质层（30），栅电极（40）以及源极和漏极区（70）的MOS晶体管结构。在MOS晶体管结构上方形成有第一和第三介质层（110），（120）和（130）。去除第二和第三介电结构（120）（130），留下具有应力沟道区的MOS晶体管，导致改善的沟道迁移特性。

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