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71. 发明申请

US20140013089A1 CONDITIONAL LOAD INSTRUCTIONS IN AN OUT-OF-ORDER EXECUTION MICROPROCESSOR 有权
标题翻译：不合格执行微处理器的条件负载指令
公开(公告)号：US20140013089A1
公开(公告)日：2014-01-09
申请号：US14007077
申请日：2012-04-06
申请人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Gerard M. Col , Colin Eddy
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30043 , G06F9/30072 , G06F9/30076 , G06F9/30174 , G06F9/30189
摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.
摘要翻译：微处理器指令转换器将条件加载指令转换成至少两个微指令。无序执行管线执行微指令。为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果，这是以前的目标寄存器值，如果没有。目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

72. 发明授权

US08522354B2 Microprocessor apparatus for secure on-die real-time clock 有权
标题翻译：用于安全的即插即用时钟的微处理器
公开(公告)号：US08522354B2
公开(公告)日：2013-08-27
申请号：US12263168
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus including a microprocessor and an external crystal. The microprocessor executes non-secure application programs and a secure application program, where the secure application program comprises instructions from a host architecture instruction set, and where the non-secure application programs are accessed from a system memory via a system bus and the secure application program is accessed from a secure non-volatile memory via a private bus coupled to the microprocessor. The microprocessor has a secure real time clock that provides a persistent time, where the secure real time clock is only visible and accessible by the secure application program when the microprocessor is executing in a secure mode. The external crystal is coupled to the secure real time clock within the microprocessor and is configured to cause an oscillator within the secure real time clock to generate an oscillating output voltage that is proportional to the frequency of the external crystal.
摘要翻译：一种包括微处理器和外部晶体的装置。微处理器执行非安全应用程序和安全应用程序，其中安全应用程序包括来自主机架构指令集的指令，并且其中通过系统总线和安全应用程序从系统存储器访问非安全应用程序通过耦合到微处理器的专用总线从安全的非易失性存储器访问程序。微处理器具有安全的实时时钟，其提供持久时间，其中安全实时时钟仅在微处理器以安全模式执行时由安全应用程序可见并可访问。外部晶体耦合到微处理器内的安全实时时钟，并被配置为使安全实时时钟内的振荡器产生与外部晶体频率成比例的振荡输出电压。

73. 发明授权

US08402279B2 Apparatus and method for updating set of limited access model specific registers in a microprocessor 有权
标题翻译：用于更新微处理器中有限访问模式特定寄存器的集合的装置和方法
公开(公告)号：US08402279B2
公开(公告)日：2013-03-19
申请号：US12391781
申请日：2009-02-24
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F9/322 , G06F9/226 , G06F9/268 , G06F9/3001 , G06F9/328 , G06F21/6209 , G06F21/72
摘要： A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected.
摘要翻译：具有模型特定寄存器（MSR）的微处理器对于每个MSR包括指示MSR是受保护还是不受保护的相关联的默认值以及相关联的熔丝，如果被熔断，则将相关联的默认值从受保护转换为非受保护或未受保护。在一个实施例中，响应于微处理器遇到访问指定MSR的指令执行以下操作的微代码：确定与指定的MSR相关联的保险丝是否被吹送或未吹出，使用与MSR相关联的默认值作为是否如果相关的保险丝未被吹出，则MSR被保护; 如果相关联的保险丝熔断，则切换相关的默认值以生成指示器; 如果指示灯指示MSR受到保护，则保护对MSR的访问; 并且如果指示符表示MSR未被保护，则不能保护对MSR的访问。

74. 发明授权

US08375078B2 Fast floating point result forwarding using non-architected data format 有权
标题翻译：使用非架构化数据格式的快速浮点结果转发
公开(公告)号：US08375078B2
公开(公告)日：2013-02-12
申请号：US12820578
申请日：2010-06-22
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/3824
摘要： A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands.
摘要翻译：具有指定集架构（ISA）的微处理器，其指定用于浮点操作数的至少一个架构数据格式（ADF）。微处理器包括多个浮点单元，每个浮点单元包括被配置为接收非ADF源操作数并且对非ADF源操作数执行浮点运算以产生非ADF结果的算术单元。微处理器还包括转发总线，其配置为将多个浮点单元的每个运算单元产生的非ADF结果转发到多个浮点单元中的每一个，以供选择性使用，作为非ADF源操作数之一。

75. 发明授权

US08341419B2 Apparatus and method for limiting access to model specific registers in a microprocessor 有权
标题翻译：用于限制访问微处理器中的模型特定寄存器的装置和方法
公开(公告)号：US08341419B2
公开(公告)日：2012-12-25
申请号：US12781087
申请日：2010-05-17
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F21/00
CPC分类号： G06F21/72
摘要： A microprocessor having a control register to which the manufacturer of the microprocessor may limit access. The microprocessor includes a manufacturing identifier that uniquely identifies the microprocessor and that is externally readable from the microprocessor by a user. The microprocessor also includes a secret key, manufactured internally within the microprocessor and externally invisible. The microprocessor also includes an encryption engine, coupled to the secret key, configured to decrypt a user-supplied password using the secret key to generate a decrypted result in response to a user instruction instructing the microprocessor to access the control register. The user-supplied password is unique to the microprocessor. The microprocessor also includes an execution unit, coupled to the manufacturing identifier and the encryption engine, configured to allow the instruction access to the control register if the manufacturing identifier is included in the decrypted result, and to otherwise deny the instruction access to the control register.
摘要翻译：具有控制寄存器的微处理器，微处理器的制造商可以将其限制访问。微处理器包括唯一地识别微处理器并且由用户从微处理器外部读取的制造标识符。微处理器还包括一个秘密密钥，内部在微处理器内制造，并且外部不可见。微处理器还包括耦合到秘密密钥的加密引擎，用于响应于指示微处理器访问控制寄存器的用户指令，使用秘密密钥解密用户提供的密码以产生解密结果。用户提供的密码对于微处理器是唯一的。微处理器还包括耦合到制造标识符和加密引擎的执行单元，其被配置为如果制造标识符被包括在解密结果中，则允许对控制寄存器的指令访问，否则拒绝对控制寄存器的指令访问。

76. 发明申请

US20120260071A1 CONDITIONAL ALU INSTRUCTION CONDITION SATISFACTION PROPAGATION BETWEEN MICROINSTRUCTIONS IN READ-PORT LIMITED REGISTER FILE MICROPROCESSOR 有权
标题翻译：条件ALU指令条件在READ-PORT有限公司注册文件微处理器中的微指令之间的满意度传播
公开(公告)号：US20120260071A1
公开(公告)日：2012-10-11
申请号：US13333631
申请日：2011-12-21
申请人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
发明人： G. Glenn Henry , Gerard M. Col , Rodney E. Hooker , Terry Parks
IPC分类号： G06F9/312 , G06F9/38 , G06F9/345 , G06F9/315
CPC分类号： G06F9/30189 , G06F9/30072 , G06F9/30123 , G06F9/30174
摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.
摘要翻译：架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。硬件指令翻译器将架构指令转换为第一和第二微指令。为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

77. 发明授权

US08245017B2 Pipelined microprocessor with normal and fast conditional branch instructions 有权
标题翻译：流水线微处理器，具有正常和快速的条件分支指令
公开(公告)号：US08245017B2
公开(公告)日：2012-08-14
申请号：US12481118
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a first branch condition state and a second branch condition state. The microprocessor also includes a conditional branch instruction of a first type that instructs the microprocessor to wait to correctly resolve the conditional branch instruction of the first type based on the first branch condition state until other instructions within the microprocessor that update the first branch condition state and that are older than the conditional branch instruction of the first type have updated the first branch condition state. A conditional branch instruction of a second type instructs the microprocessor to correctly resolve the conditional branch instruction of the second type based on the second branch condition state without regard to whether other instructions within the microprocessor that update the second branch condition state and that are older than the conditional branch instruction of the second type have yet updated the second branch condition state.
摘要翻译：微处理器包括第一分支状态和第二分支状态。微处理器还包括第一类型的条件转移指令，指示微处理器基于第一转移条件状态等待正确地解析第一类型的条件转移指令，直到微处理器内的其他指令更新第一分支状态和比第一类型的条件分支指令更旧的第一分支条件状态。第二类型的条件分支指令指示微处理器基于第二分支条件状态来正确地解析第二类型的条件分支指令，而不考虑微处理器内是否更新第二分支条件状态并且比第二分支状态更新的其它指令第二类型的条件分支指令还更新了第二分支条件状态。

78. 发明授权

US08234543B2 Detection and correction of fuse re-growth in a microprocessor 有权
标题翻译：微处理器中保险丝再生长的检测和校正
公开(公告)号：US08234543B2
公开(公告)日：2012-07-31
申请号：US12609207
申请日：2009-10-30
申请人： G. Glenn Henry , Charles John Holthaus , Terry Parks
发明人： G. Glenn Henry , Charles John Holthaus , Terry Parks
IPC分类号： G06F11/00
CPC分类号： G11C17/18 , G06F11/1048 , G11C2029/0411
摘要： A microprocessor includes control hardware that receives and stores control values and provides the control values to circuits of the microprocessor for controlling operation of the microprocessor. The microprocessor also includes a first plurality of fuses selectively blown collectively with a predetermined value, and a second plurality of fuses selectively blown collectively with an error correction value computed from the predetermined value collectively blown into the first plurality of fuses. In response to being reset, the microprocessor reads the first and second plurality of fuses, detects an error in the value read from the first plurality of fuses using the value read from the second plurality of fuses, corrects the value read from the first plurality of fuses back to the predetermined value using the value read from the second plurality of fuses, and uses the corrected predetermined value to write the control values into the control hardware.
摘要翻译：微处理器包括控制硬件，其接收并存储控制值，并将控制值提供给微处理器的电路以控制微处理器的操作。微处理器还包括以预定值一起共同选择性地熔断的第一组多个熔丝，以及第二多个熔丝，其以从共同吹制到第一组熔丝中的预定值计算的误差校正值一起共同选择性地吹制。响应于复位，微处理器读取第一和第二多个保险丝，使用从第二多个保险丝读取的值检测从第一多个保险丝读取的值中的错误，校正从第一多个保险丝读取的值使用从第二多个保险丝读取的值将保险丝恢复到预定值，并且使用校正的预定值将控制值写入控制硬件。

79. 发明授权

US08209763B2 Processor with non-volatile mode enable register entering secure execution mode and encrypting secure program for storage in secure memory via private bus 有权
标题翻译：具有非易失性模式的处理器使能寄存器进入安全执行模式，并通过专用总线加密安全程序以存储在安全存储器中
公开(公告)号：US08209763B2
公开(公告)日：2012-06-26
申请号：US12263221
申请日：2008-10-31
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F12/1408 , G06F21/12 , G06F21/14 , G06F21/554 , G06F21/70 , G06F21/71 , G06F21/73 , G06F21/74 , G06F21/75 , G06F21/82
摘要： An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor is a single integrated circuit disposed on a single die, and executes non-secure application programs and a secure application program. The secure application program is executed in a secure execution mode. The non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-volatile enabled indicator register that is configured indicate whether the microprocessor is within the secure execution mode or a non-secure execution mode, where contents of the non-volatile enabled indicator register persist through power removal and reapplication to the microprocessor. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
摘要翻译：一种包括微处理器和安全非易失性存储器的装置。微处理器是单个集成电路，设置在单个管芯上，并执行非安全应用程序和安全应用程序。安全应用程序以安全执行模式执行。通过系统总线从系统存储器访问非安全应用程序。微处理器具有非易失性使能指示符寄存器，其被配置为指示微处理器是处于安全执行模式还是非安全执行模式，其中非易失性使能指示符寄存器的内容通过电力消除持续并重新应用于微处理器。安全非易失性存储器经由专用总线耦合到微处理器，并被配置为存储安全应用程序，其中微处理器和安全非易失性存储器之间的专用总线上的事务与系统总线和对应的系统隔离微处理器内的总线资源。

80. 发明申请

US20110035617A1 USER-INITIATABLE METHOD FOR DETECTING RE-GROWN FUSES WITHIN A MICROPROCESSOR 有权
标题翻译：用于在微处理器中检测再熔融熔融物的用户可触发的方法
公开(公告)号：US20110035617A1
公开(公告)日：2011-02-10
申请号：US12719291
申请日：2010-03-08
申请人： G. Glenn Henry , Terry Parks
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F11/07
CPC分类号： G06F11/10 , G06F11/2236
摘要： A microprocessor includes a first plurality of fuses, selectively blown with a predetermined value for provision to circuits of the microprocessor to control operation of the microprocessor. The microprocessor also includes a second plurality of fuses, selectively blown with error detection information used to detect an error in the first plurality of fuses such that a blown fuse of the microprocessor returned a non-blown binary value. In response to a user program instruction, the microprocessor is configured to determine whether there is an error in the first plurality of fuses such that a blown fuse returned a non-blown binary value using the error detection information from the second plurality of fuses.
摘要翻译：微处理器包括第一组多个保险丝，其被选择性地以预定值吹送，以供给微处理器的电路以控制微处理器的操作。微处理器还包括第二多个保险丝，其选择性地吹制有用于检测第一多个保险丝中的错误的错误检测信息，使得微处理器的保险丝熔断器返回非发送的二进制值。响应于用户程序指令，微处理器被配置为确定在第一多个保险丝中是否存在错误，使得熔丝熔丝使用来自第二多个保险丝的错误检测信息返回未熔二进制值。

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