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1. 发明授权

US08671285B2 Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions 有权
标题翻译：微处理器在纯文本指令的同时提取和解密加密的指令
公开(公告)号：US08671285B2
公开(公告)日：2014-03-11
申请号：US13091487
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.
摘要翻译：提取单元（a）从微处理器的指令高速缓冲存储器获取指令数据块; （b）使用数据实体在块上执行异或以产生明文指令数据; 和（c）将明文指令数据提供给指令译码单元。在第一种情况下，块包括加密指令数据，数据实体是解密密钥。在第二种情况下，该块包括未加密的指令数据，并且数据实体为布尔零。执行（a），（b）和（c）所需的时间在第一和第二实例中是相同的，而不管该块是加密还是未加密。解密密钥生成器从多个密钥中选择第一和第二密钥，旋转第一密钥，并且基于获取地址的部分，将旋转后的第一密钥加到/从第二密钥中加减乘以产生解密密钥。

2. 发明授权

US08131984B2 Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state 有权
标题翻译：流水线微处理器，具有基于静态串行化指令状态的快速条件分支指令
公开(公告)号：US08131984B2
公开(公告)日：2012-03-06
申请号：US12481499
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.
摘要翻译：微处理器包括控制寄存器，其存储影响微处理器的操作的控制值。指令集架构包括基于存储在控制寄存器中的控制值来指定分支条件的条件转移指令，以及更新控制寄存器中的控制值的串行化指令。微处理器通过串行化指令之前的指令完成对标志，寄存器和存储器的所有修改，并在串行化指令之前取出并执行下一条指令，将所有缓冲写入消耗到存储器中。响应串行化指令，执行单元更新控制寄存器中的控制值。取出单元基于存储在控制寄存器中的控制值来取得，解码和无条件地正确地解析和退出条件转移指令，而不是将条件转移指令分派到要解析的执行单元。

3. 发明授权

US07975132B2 Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor 有权
标题翻译：在存在流水线微处理器中的推测性条件指令执行的情况下，使用多个调用/返回堆栈快速正确解析呼叫和返回指令的装置和方法
公开(公告)号：US07975132B2
公开(公告)日：2011-07-05
申请号：US12481074
申请日：2009-06-09
申请人： Brent Bean , Terry Parks , G. Glenn Henry
发明人： Brent Bean , Terry Parks , G. Glenn Henry
IPC分类号： G06F9/38
CPC分类号： G06F9/30054 , G06F9/3806 , G06F9/3844
摘要： A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.
摘要翻译：具有多个呼叫/返回栈（CRS）的微处理器正确地解析了呼叫或返回指令，而不是向要解析的微处理器的执行单元发出指令。微处理器获取一个调用或返回指令，并确定该指令是否是在获取尚未解决的条件分支指令之后获取的第一个调用或返回指令。如果状态存在，则微处理器将当前CRS的内容复制到另一个CRS，并将其他CRS指定为当前CRS。如果指令是呼叫指令，微处理器将呼叫指令之后的下一个顺序指令的地址推送到当前CRS上，并在调用指令目标地址处取指令。如果指令是返回指令，则微处理器从当前CRS中弹出第二个返回地址，并在第二个返回地址处获取指令。

4. 发明申请

US20100205404A1 PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC MICROCODE-IMPLEMENTED INSTRUCTION STATE 有权
标题翻译：具有快速条件分支指令的管道微处理器基于静态微处理器实施指令状态
公开(公告)号：US20100205404A1
公开(公告)日：2010-08-12
申请号：US12481487
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/312 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.
摘要翻译：微处理器包括存储器，其存储非用户程序的指令以实现微处理器的用户可见指令集的用户程序指令。非用户程序包括条件分支指令。第一提取单元获取包括由非用户程序实现的指令的用户程序的指令。指令解码器对用户程序指令进行解码，并且响应于解码由非用户程序实现的用户程序指令而保存状态。执行单元执行由第一取出单元取出的用户程序指令，并执行非条件转移指令以外的非用户程序的指令。第二取出单元从存储器取出非用户程序指令，并且基于保存的状态解析条件转移指令，而不向执行单元发送条件转移指令来解析条件转移指令。

5. 发明申请

US20110296205A1 MICROPROCESSOR THAT FACILITATES TASK SWITCHING BETWEEN MULTIPLE ENCRYPTED PROGRAMS HAVING DIFFERENT ASSOCIATED DECRYPTION KEY VALUES 有权
标题翻译：微处理器在多个加密程序之间进行任务切换，具有不同的相关分解键值
公开(公告)号：US20110296205A1
公开(公告)日：2011-12-01
申请号：US13091785
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F12/14
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor includes a storage element having a plurality of locations each storing decryption key data associated with an encrypted program. A control register field (may be x86 EFLAGS register reserved field) specifies a storage element location associated with a currently executing encrypted program. The microprocessor restores from memory to the control register a previously saved value of the field in response to executing a return from interrupt instruction. A fetch unit fetches encrypted instructions of the currently executing encrypted program and decrypts them using the decryption key data stored the storage element location specified by the restored field value. A kill bit associated with each storage element location may be employed if the location is clobbered because more encrypted programs are multitasked than available locations in the storage element, in which case an exception is generated to re-load the clobbered decryption key data in response to the return from interrupt instruction.
摘要翻译：微处理器包括具有多个位置的存储元件，每个位置存储与加密程序相关联的解密密钥数据。控制寄存器字段（可以是x86 EFLAGS寄存器保留字段）指定与当前执行的加密程序相关联的存储元件位置。响应于执行中断指令的返回，微处理器从存储器恢复到控制寄存器先前保存的字段值。提取单元获取当前执行的加密程序的加密指令，并使用存储由恢复的字段值指定的存储单元位置的解密密钥数据进行解密。如果位置被破坏，则可以采用与每个存储元件位置相关联的杀死位，因为更多的加密程序比存储元件中的可用位置多任务，在这种情况下生成异常以重新加载被破译的解密密钥数据，以响应于从中断指令返回。

6. 发明申请

US20100228952A1 APPARATUS AND METHOD FOR FAST CORRECT RESOLUTION OF CALL AND RETURN INSTRUCTIONS USING MULTIPLE CALL/RETURN STACKS IN THE PRESENCE OF SPECULATIVE CONDITIONAL INSTRUCTION EXECUTION IN A PIPELINED MICROPROCESSOR 有权
标题翻译：使用多个呼叫/返回堆栈进行呼叫和返回指令的快速更正分辨率的装置和方法在管道微处理器中的规范条件指令执行中存在
公开(公告)号：US20100228952A1
公开(公告)日：2010-09-09
申请号：US12481074
申请日：2009-06-09
申请人： Brent Bean , Terry Parks , G. Glenn Henry
发明人： Brent Bean , Terry Parks , G. Glenn Henry
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/3806 , G06F9/3844
摘要： A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.
摘要翻译：具有多个呼叫/返回栈（CRS）的微处理器正确地解析了呼叫或返回指令，而不是向要解析的微处理器的执行单元发出指令。微处理器获取一个调用或返回指令，并确定该指令是否是在获取尚未解决的条件分支指令之后获取的第一个调用或返回指令。如果状态存在，则微处理器将当前CRS的内容复制到另一个CRS，并将其他CRS指定为当前CRS。如果指令是呼叫指令，微处理器将呼叫指令之后的下一个顺序指令的地址推送到当前CRS上，并在调用指令目标地址处取指令。如果指令是返回指令，则微处理器从当前CRS中弹出第二个返回地址，并在第二个返回地址处获取指令。

7. 发明申请

US20100228950A1 MICROPROCESSOR WITH FAST EXECUTION OF CALL AND RETURN INSTRUCTIONS 有权
标题翻译： MICROPROCESSOR与快速执行的呼叫和返回指示
公开(公告)号：US20100228950A1
公开(公告)日：2010-09-09
申请号：US12481199
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/3806 , G06F9/3844
摘要： A microprocessor includes an instruction set architecture, comprising a call instruction type, a return instruction type, and other instruction types. Execution units correctly execute program instructions of the other instruction types. A call/return stack has a plurality of entries arranged in a last-in-first-out manner. The call/return stack is architectural state of the microprocessor not modifiable by program instructions of the other instruction types. The call/return stack is architectural state of the microprocessor indirectly modifiable by program instructions of the call and return instruction types. The microprocessor also includes a fetch unit that fetches program instructions and sends the program instructions of the other instruction types to the execution units to be correctly executed. The fetch unit correctly executes program instructions of the call and return instruction types without sending the program instructions of the call and return instruction types to the execution units to be correctly executed.
摘要翻译：微处理器包括指令集架构，其包括调用指令类型，返回指令类型和其他指令类型。执行单元正确执行其他指令类型的程序指令。呼叫/返回栈具有以先进先出方式排列的多个条目。调用/返回栈是微处理器的架构状态，不能通过其他指令类型的程序指令进行修改。调用/返回栈是通过调用和返回指令类型的程序指令间接修改的微处理器的架构状态。微处理器还包括提取单元，其取得程序指令，并将其他指令类型的程序指令发送到执行单元以进行正确执行。提取单元正确地执行调用和返回指令类型的程序指令，而不将调用的程序指令和返回指令类型发送到要正确执行的执行单元。

8. 发明申请

US20100205415A1 PIPELINED MICROPROCESSOR WITH FAST CONDITIONAL BRANCH INSTRUCTIONS BASED ON STATIC SERIALIZING INSTRUCTION STATE 有权
标题翻译：基于静态串行指令状态的快速条件分支指令的管道微处理器
公开(公告)号：US20100205415A1
公开(公告)日：2010-08-12
申请号：US12481499
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/38
CPC分类号： G06F9/30058 , G06F9/3867
摘要： A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.
摘要翻译：微处理器包括控制寄存器，其存储影响微处理器的操作的控制值。指令集架构包括基于存储在控制寄存器中的控制值来指定分支条件的条件转移指令，以及更新控制寄存器中的控制值的串行化指令。微处理器通过串行化指令之前的指令完成对标志，寄存器和存储器的所有修改，并在串行化指令之前取出并执行下一条指令，将所有缓冲写入消耗到存储器中。响应串行化指令，执行单元更新控制寄存器中的控制值。取出单元基于存储在控制寄存器中的控制值来取得，解码和无条件地正确地解析和退出条件转移指令，而不是将条件转移指令分派到要解析的执行单元。

9. 发明申请

US20100205401A1 PIPELINED MICROPROCESSOR WITH FAST NON-SELECTIVE CORRECT CONDITIONAL BRANCH INSTRUCTION RESOLUTION 有权
标题翻译：具有快速非选择性正确条件分支指令解决方案的管道微处理器
公开(公告)号：US20100205401A1
公开(公告)日：2010-08-12
申请号：US12481035
申请日：2009-06-09
申请人： G. Glenn Henry , Terry Parks , Brent Bean
发明人： G. Glenn Henry , Terry Parks , Brent Bean
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/3802 , G06F9/3867
摘要： A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state. The fetch unit also non-selectively refrains from sending the conditional branch instruction to the execution units to be resolved regardless of whether the execution units have updated the register state.
摘要翻译：微处理器包括存储状态的寄存器和取得程序指令的读取单元。该程序包括非紧接在第二条指令之后的第一条指令。第一条指令指示微处理器更新寄存器中的状态。第二条指令是指定基于寄存器状态的分支条件的条件分支指令。提取单元调度第一条指令执行，但是不执行第二条指令执行。执行单元从提取单元接收第一个指令，并响应更新寄存器状态。当执行单元更新寄存器状态时，取出单元基于寄存器状态非选择性地正确地解析条件转移指令。无论执行单元是否更新了寄存器状态，提取单元还非选择性地禁止将条件转移指令发送到待解析的执行单元。

10. 发明授权

US08700919B2 Switch key instruction in a microprocessor that fetches and decrypts encrypted instructions 有权
标题翻译：在提取和解密加密指令的微处理器中切换密钥指令
公开(公告)号：US08700919B2
公开(公告)日：2014-04-15
申请号：US13091547
申请日：2011-04-21
申请人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00
CPC分类号： H04L9/0827 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/72 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A fetch unit fetches a sequence of blocks of encrypted instructions of an encrypted program from an instruction cache at a corresponding sequence of fetch address values. While fetching each block of the sequence, the fetch unit generates a decryption key as a function of key values and the corresponding fetch address value, and decrypts the encrypted instructions using the generated decryption key by XORing them together. A switch key instruction instructs the microprocessor to update the key values in the fetch unit while the fetch unit is fetching the sequence of blocks. The fetch unit inherently provides an effective decryption key length that depends upon the function and amount of key values used. Including one or more switch key instructions within the encrypted program increases the effective decryption key length up to the encrypted program length.
摘要翻译：取出单元以相应的获取地址值序列从指令高速缓存中提取加密程序的加密指令的一系列块。在提取序列的每个块时，提取单元根据密钥值和相应的获取地址值产生解密密钥，并且通过将它们一起进行异或来解密加密的指令。切换键指令指示微处理器在获取单元获取块序列时更新提取单元中的键值。提取单元固有地提供了一个有效的解密密钥长度，这取决于所使用的密钥值的功能和数量。在加密程序中包括一个或多个切换密钥指令将有效的解密密钥长度增加到加密的程序长度。

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