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71. 发明申请

US20080230846A1 METHOD OF MANUFACTURING METAL SILICIDE CONTACTS 有权
标题翻译：制造金属硅化物接触的方法
公开(公告)号：US20080230846A1
公开(公告)日：2008-09-25
申请号：US11690643
申请日：2007-03-23
申请人： Yaw S. Obeng , Juanita DeLoach , Freidoon Mehrad
发明人： Yaw S. Obeng , Juanita DeLoach , Freidoon Mehrad
IPC分类号： H01L29/76 , H01L21/44 , H01L29/94 , H01L21/461 , H01L21/302 , H01L31/00
CPC分类号： H01L21/823835 , H01L21/02068 , H01L21/28518 , H01L21/823871
摘要： A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底表面上形成金属硅化物栅电极。该方法还包括将金属硅化物栅电极和衬底表面暴露于清洁过程。清洁过程包括使用含无水氟化物的进料气体的干等离子体蚀刻和被配置为使金属硅化物栅电极基本上保持不变的热升华。该方法还包括在衬底表面的源极和漏极区域上沉积金属层并退火衬底表面的金属层和源极和漏极区域以形成金属硅化物源极和漏极接触。

72. 发明申请

US20080176345A1 Ebeam inspection for detecting gate dielectric punch through and/or incomplete silicidation or metallization events for transistors having metal gate electrodes 审中-公开
标题翻译：用于检测栅极电介质穿透的Ebeam检查和/或用于具有金属栅电极的晶体管的不完全硅化或金属化事件
公开(公告)号：US20080176345A1
公开(公告)日：2008-07-24
申请号：US11655483
申请日：2007-01-19
申请人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
发明人： Shaofeng Yu , Richard L. Guldi , Jiong-Ping Lu , Freidoon Mehrad , Jae Hyun Park
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： Gate dielectric punch through and/or incomplete silicidation or metallization events that may occur during transistor formation are identified. The events are identified just after gate electrodes are formed in order to characterize the degree of faulty transistors for process control purposes and to scrap product if sufficiently defective so that subsequent resources are not unnecessarily expended. An electron beam or ebeam is directed at locations of a workpiece whereon on or more transistors are formed. Electrons that are resultantly emitted from these locations are detected and used to develop respective gray level values (GLV's). Gate dielectric punch through and/or incomplete silicidation or metallization events are identified by finding high or low GLV's relative to neighboring areas.
摘要翻译：识别在晶体管形成期间可能发生的栅极电介质穿透和/或不完全的硅化或金属化事件。在形成栅极电极之后才识别事件，以便表征用于过程控制目的的故障晶体管的程度，并且如果充分有缺陷，则废弃产品，使得后续资源不会被不必要地消耗。电子束或ebeam被引导到其上形成有多个晶体管的工件的位置。从这些位置发射的电子被检测并用于开发各自的灰度值（GLV's）。通过相对于相邻区域发现高或低GLV来鉴定栅极电介质穿透和/或不完全硅化或金属化事件。

73. 发明申请

US20070066007A1 Method to obtain fully silicided gate electrodes 有权
标题翻译：获得完全硅化栅电极的方法
公开(公告)号：US20070066007A1
公开(公告)日：2007-03-22
申请号：US11228902
申请日：2005-09-16
申请人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在位于栅电极（250）之间的间隔材料（415）和位于栅电极（250）之间的掺杂区域（255）之间沉积保护层（510），去除间隔物的一部分材料（415）和位于栅电极（250）上方的保护层（510）。间隔材料（415）的剩余部分保留在栅电极（250）的顶表面上方并且在掺杂区域（255）之上，并且保护层（510）的一部分保留在掺杂区域（255）上方。该方法还包括去除间隔物材料（415）的剩余部分以在栅电极（250）上形成间隔壁侧壁，露出栅电极（250）的顶表面，并留下间隔物材料（415）的残留物在掺杂区域（255）上。源极/漏极形成在栅电极250附近并且通过间隔物材料（415）的残留物，并且金属被结合到栅电极（250）中。

74. 发明申请

US20050247994A1 Shallow trench isolation structure and method 审中-公开
公开(公告)号：US20050247994A1
公开(公告)日：2005-11-10
申请号：US11178935
申请日：2005-07-11
申请人： Freidoon Mehrad , Zhihao Chen , Shashank Ekbote , Brian Trentman
发明人： Freidoon Mehrad , Zhihao Chen , Shashank Ekbote , Brian Trentman
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224
摘要： Disclosed is a shallow trench isolation (STI) structure and methods of manufacturing the same. The methods eliminate the requirement for design size adjustments (DSA) in manufacturing the STI structure. Further disclosed is an STI trench liner and methods for the formation thereof by growing a thin oxide layer on shallow isolation trench surfaces while preventing oxide formation on adjacent nitride surfaces, followed by the deposition of, and oxide growth upon, a polysilicon layer.

75. 发明申请

US20050164431A1 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US20050164431A1
公开(公告)日：2005-07-28
申请号：US11072779
申请日：2005-03-04
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

76. 发明申请

US20050062127A1 Method to form shallow trench isolation with rounded upper corner for advanced semiconductor circuits 有权
公开(公告)号：US20050062127A1
公开(公告)日：2005-03-24
申请号：US10691843
申请日：2003-10-23
申请人： Zhihao Chen , Freidoon Mehrad , Brian Kirkpatrick , Jeff White , Edmund Russell , Jon Holt , Jason Mehigan
发明人： Zhihao Chen , Freidoon Mehrad , Brian Kirkpatrick , Jeff White , Edmund Russell , Jon Holt , Jason Mehigan
IPC分类号： H01L21/316 , H01L21/762 , H01L29/00
CPC分类号： H01L21/02126 , H01L21/02236 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76235
摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

77. 发明授权

US06706605B1 Transistor formed from stacked disposable sidewall spacer 有权
标题翻译：由堆叠的一次性侧壁间隔物形成的晶体管
公开(公告)号：US06706605B1
公开(公告)日：2004-03-16
申请号：US10403065
申请日：2003-03-31
申请人： Shashank S. Ekbote , Freidoon Mehrad
发明人： Shashank S. Ekbote , Freidoon Mehrad
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit transistor (80), comprising providing a semiconductor region (90) and forming a gate structure (92, 94) in a fixed position relative to the semiconductor region. The gate structure has a first sidewall (94a) and a second sidewall (94b). The method also comprises first, forming a first layer (96) adjacent the first sidewall and the second sidewall, and second, forming a second layer (98) adjacent the first layer. The method also comprises third, forming a third layer (100) adjacent the second layer, and fourth, forming a fourth layer (102) adjacent the third layer. The method also comprises fifth, implanting a first and second source/drain region (106a, 106b) in the semiconductor region and at a first distance laterally with respect to the gate structure, wherein a combined thickness of the first, second, third, and fourth layers determines the first distance. The method also comprises sixth, removing the third and fourth layers, and seventh, implanting a third and fourth source/drain region (108a, 108b) in the semiconductor region and at a second distance laterally with respect to the gate structure, wherein the second distance is less than the first distance.
摘要翻译：一种形成集成电路晶体管（80）的方法，包括提供半导体区域（90）并形成相对于半导体区域固定位置的栅极结构（92,94）。栅极结构具有第一侧壁（94a）和第二侧壁（94b）。该方法还包括首先形成邻近第一侧壁和第二侧壁的第一层（96），其次形成邻近第一层的第二层（98）。该方法还包括第三，形成与第二层相邻的第三层（100），第四层形成与第三层相邻的第四层（102）。该方法还包括第五步，在半导体区域中以相对于栅极结构横向第一距离注入第一和第二源/漏区（106a，106b），其中第一，第二，第三和第第四层确定第一距离。该方法还包括第六层，去除第三层和第四层，以及第七层，在半导体区域和相对于栅极结构的横向第二距离处注入第三和第四源/漏区（108a，108b），其中第二距离小于第一距离。

78. 发明授权

US06677766B2 Shallow trench isolation step height detection method 有权
标题翻译：浅沟隔离步距检测方法
公开(公告)号：US06677766B2
公开(公告)日：2004-01-13
申请号：US10044083
申请日：2001-10-26
申请人： Freidoon Mehrad , Kayvan Sadra , Yaojian Leng
发明人： Freidoon Mehrad , Kayvan Sadra , Yaojian Leng
IPC分类号： G01R2708
CPC分类号： H01L22/34
摘要： A method for measuring the step height of a STI structure is described. The method involves measuring the change in resistance of a polysilicon structure as the step height changes. The resistance of the polysilicon structure is measured by applying a voltage and measuring the resulting current.
摘要翻译：描述了用于测量STI结构的台阶高度的方法。该方法包括随着台阶高度的变化来测量多晶硅结构的电阻变化。通过施加电压并测量所得到的电流来测量多晶硅结构的电阻。

79. 发明授权

US06566200B2 Flash memory array structure and method of forming 有权
公开(公告)号：US06566200B2
公开(公告)日：2003-05-20
申请号：US10176139
申请日：2002-06-20
申请人： Freidoon Mehrad , Suresh Potla , Zhihao Chen
发明人： Freidoon Mehrad , Suresh Potla , Zhihao Chen
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of forming a flash memory array structure includes forming a first dielectric layer outwardly from a semiconductor substrate, removing a portion of the first dielectric layer and the substrate to create a trench isolation region, forming a second dielectric layer in the trench isolation region, removing a portion of the second dielectric layer to create an exposed substrate region proximate a bottom of the trench isolation region, doping the exposed substrate region with an n-type dopant, and forming a silicide region in the exposed substrate region.

80. 发明授权

US06348370B1 Method to fabricate a self aligned source resistor in embedded flash memory applications 有权
标题翻译：在嵌入式闪存应用中制造自对准源电阻的方法
公开(公告)号：US06348370B1
公开(公告)日：2002-02-19
申请号：US09610274
申请日：2000-07-06
申请人： Freidoon Mehrad , Harold D. Goodpaster , Anand Seshadri
发明人： Freidoon Mehrad , Harold D. Goodpaster , Anand Seshadri
IPC分类号： H01L218234
CPC分类号： H01L28/24 , H01L27/11531
摘要： A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate array (9) is formed on a semiconductor substrate. Isolations regions (70) are removed and the exposed silicon implanted forming diffused regions (180). The SAS so formed can be configured to function as a resistor element (240).
摘要翻译：描述了在嵌入式FLASH存储器应用中制造半导体电阻器的方法。在该方法中，在半导体衬底上形成栅极阵列（9）。剥离区域（70）并且暴露的硅注入形成扩散区域（180）。如此形成的SAS可被配置为用作电阻元件（240）。

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