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71. 发明授权

US06889300B2 Memory system and method for two step write operations 失效
标题翻译：用于两步写入操作的内存系统和方法
公开(公告)号：US06889300B2
公开(公告)日：2005-05-03
申请号：US10014457
申请日：2001-12-11
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F13/16 , G11C5/00 , G11C7/10 , G11C7/22 , G06F12/06
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.
摘要翻译：描述了一种用于将数据存储在存储器件中的方法和装置。该装置被配置为执行以下步骤。该方法采用两步技术，允许无序完成读写操作。当写入操作需要完成读取操作所需的资源时，被写入的数据被存储在存储器件中的写入数据缓冲器中。写入数据被存储在缓冲器中，直到数据路径可用于将数据传送到存储器件的存储器核心。一旦资源空闲（或存储设备或其控制器强制写入完成），数据将使用现在免费的数据路径写入存储器设备的存储器内核。

72. 发明授权

US06868474B2 High performance cost optimized memory 失效
公开(公告)号：US06868474B2
公开(公告)日：2005-03-15
申请号：US10128167
申请日：2002-04-22
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G11C7/10 , G11C7/12 , G11C11/4096 , G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

73. 发明授权

US06842864B1 Method and apparatus for configuring access times of memory devices 失效
标题翻译：用于配置存储设备的访问时间的方法和装置
公开(公告)号：US06842864B1
公开(公告)日：2005-01-11
申请号：US09685014
申请日：2000-10-05
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time. A delay is programmed in at least one register of each of the DRAM devices coupled to the bus by writing values to at least one register of each of the DRAM devices.
摘要翻译：提供了用于初始化动态随机存取存储器（DRAM）装置的方法和装置，其中通过确定耦合到总线的多个DRAM装置中的每一个的响应时间来对信道进行均衡化。确定DRAM设备的响应时间包括使用总线将逻辑1写入DRAM设备的存储器位置。随后，通过总线发出读命令，其中读指令寻址到DRAM设备的新写存储位置。然后，存储器控制器测量读取命令的发出和从DRAM设备接收的逻辑电路之间的经过时间，并且该经过时间是DRAM设备的响应时间。在确定每个DRAM器件的响应时间并使用最长的响应时间之后，为耦合到总线的每个DRAM器件计算延迟，使得每个DRAM器件的时钟周期中的响应时间被耦合总线等于最长响应时间。通过将值写入至每个DRAM器件的至少一个寄存器，在连接到总线的每个DRAM器件的至少一个寄存器中编程延迟。

74. 发明授权

US06826657B1 Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权
标题翻译：增加具有不匹配内存模块的每个模块内存系统带宽的技术
公开(公告)号：US06826657B1
公开(公告)日：2004-11-30
申请号：US09948769
申请日：2001-09-10
申请人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
发明人： Frederick A. Ware , Richard E. Perego , Craig E. Hampel , Ely K. Tsern
IPC分类号： G06F1200
CPC分类号： G06F13/1684
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component having a memory core for storing data therein, a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory module also comprises access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections. The memory controller provides memory access signals to the memory module for selecting between the first mode and the second mode.
摘要翻译：公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。在一个示例性实施例中，通过包括存储器模块和存储器控制器的存储器系统来实现这些技术。存储器模块包括具有用于在其中存储数据的存储器核心的存储器组件，用于提供对存储器核心的访问的第一组接口连接以及用于提供对存储器核心的访问的第二组接口连接。存储器模块还包括访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可通过第二组接口连接访问，并且第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接访问。存储器控制器向存储器模块提供存储器访问信号，用于在第一模式和第二模式之间进行选择。

75. 发明授权

US06825841B2 Granularity memory column access 失效
标题翻译：粒度内存列访问
公开(公告)号：US06825841B2
公开(公告)日：2004-11-30
申请号：US09949464
申请日：2001-09-07
申请人： Craig E. Hampel , Richard E. Warmke , Frederick A. Ware
发明人： Craig E. Hampel , Richard E. Warmke , Frederick A. Ware
IPC分类号： G06F1576
CPC分类号： G09G5/39 , G09G5/393 , G09G2360/122
摘要： A memory device includes multiple data I/O lanes and corresponding lane or column decoders. Instead of providing the same address to each column decoder, decoder logic calculates potentially different column addresses depending on the needs of the device utilizing the memory. For example, the column addresses might be based on a received CAS address and an accompanying offset. This allows data access at alignments that do not necessarily correspond to CAS alignments. The technique is utilized in conjunction with graphics systems in which tiling is used. In systems such as this, memory offsets are specified in terms of pixel columns and rows. The technique is also used in conjunction with a router such as a TCP/IP router, in which individual packets are aligned at CAS boundaries. In this situation, the decoder logic is alternatively configurable to allow access of either an information packet or a plurality of packet headers during a single memory access cycle.
摘要翻译：存储器件包括多个数据I / O通道和相应的通道或列解码器。代替向每个列解码器提供相同的地址，解码器逻辑根据使用存储器的设备的需要来计算潜在的不同的列地址。例如，列地址可能基于接收的CAS地址和附带的偏移。这允许在不一定对应于CAS对准的对准处的数据访问。该技术与使用平铺的图形系统结合使用。在这样的系统中，以像素列和行来指定存储器偏移。该技术还与诸如TCP / IP路由器的路由器结合使用，其中各个分组在CAS边界处对齐。在这种情况下，解码器逻辑可选地可配置为允许在单个存储器访问周期期间访问信息分组或多个分组报头。

76. 发明授权

US06788593B2 Asynchronous, high-bandwidth memory component using calibrated timing elements 失效
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US06788593B2
公开(公告)日：2004-09-07
申请号：US09796924
申请日：2001-02-28
申请人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
发明人： Frederick A. Ware , Ely K. Tsern , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C700
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

77. 发明授权

US06401167B1 High performance cost optimized memory 失效
公开(公告)号：US06401167B1
公开(公告)日：2002-06-04
申请号：US09169206
申请日：1998-10-09
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

78. 发明授权

US06343352B1 Method and apparatus for two step memory write operations 失效
标题翻译：两步存储器写入操作的方法和装置
公开(公告)号：US06343352B1
公开(公告)日：2002-01-29
申请号：US09169736
申请日：1998-10-09
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F1212
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.
摘要翻译：描述了一种用于将数据存储在存储器件中的方法和装置。该装置被配置为执行以下步骤。该方法采用两步技术，允许无序完成读写操作。当写入操作需要完成读取操作所需的资源时，被写入的数据被存储在存储器件中的写入数据缓冲器中。写入数据被存储在缓冲器中，直到数据路径可用于将数据传送到存储器件的存储器核心。一旦资源空闲（或存储设备或其控制器强制写入完成），数据将使用现在免费的数据路径写入存储器设备的存储器内核。

79. 发明授权

US08644419B2 Periodic calibration for communication channels by drift tracking 有权
标题翻译：通过漂移跟踪定期通信通道
公开(公告)号：US08644419B2
公开(公告)日：2014-02-04
申请号：US13452543
申请日：2012-04-20
申请人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
发明人： Craig E. Hampel , Frederick A. Ware , Richard E. Perego
IPC分类号： H04L27/00
CPC分类号： H04B17/11 , H04B17/00 , H04B17/21 , H04L7/0004 , H04L7/0016 , H04L7/0087 , H04L7/043 , H04L7/10 , H04L27/00
摘要： A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
摘要翻译：提供执行第一校准序列的方法和系统，例如在系统初始化时，建立操作值，其利用旨在穷举的算法，并且不时地执行第二校准序列以测量在参数中漂移，并根据测量的漂移更新操作值。与第一校准序列相比，第二校准序列使用较少的通信信道资源。在一个实施例中，用于操作值的测量和收敛的第一校准序列利用长校准模式，例如大于30字节的代码，或长度为2N-1位的伪随机比特序列，其中N等于或大于而第二校准序列使用短校准模式，例如小于16字节的固定代码，例如短至2字节长。

80. 发明授权

US08504790B2 Memory component having write operation with multiple time periods 有权
标题翻译：存储器组件具有多个时间段的写入操作
公开(公告)号：US08504790B2
公开(公告)日：2013-08-06
申请号：US13424273
申请日：2012-03-19
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F13/1626 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.
摘要翻译：存储器控制器芯片执行用于将数据存储在包括具有动态随机存取存储单元的存储器核心的存储器芯片中的方法。该方法包括向存储器芯片的第一接口发送写命令，其中写命令指定写操作。在发送写命令之后，存储器控制器芯片等待与由存储芯片存储写入命令的时间段对应的第一时间段，并且将与写入操作相关联的数据发送到存储器芯片的第二接口，其中所述数据的发送在第二时间段之后发生，在所述第一时间段之后的所述第二时间段，使得发送所述写入命令并发送所述数据被隔开第一预定延迟时间，所述第一预定延迟时间包括所述第一时间段和第二个时期。

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